Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T1	7		T12	4		T10	7
all_values[1]	272	1			T1	7		T12	4		T10	7
all_values[2]	272	1			T1	7		T12	4		T10	7
all_values[3]	272	1			T1	7		T12	4		T10	7
all_values[4]	272	1			T1	7		T12	4		T10	7
all_values[5]	272	1			T1	7		T12	4		T10	7
all_values[6]	272	1			T1	7		T12	4		T10	7
all_values[7]	272	1			T1	7		T12	4		T10	7
all_values[8]	272	1			T1	7		T12	4		T10	7
all_values[9]	272	1			T1	7		T12	4		T10	7
all_values[10]	272	1			T1	7		T12	4		T10	7
all_values[11]	272	1			T1	7		T12	4		T10	7
all_values[12]	272	1			T1	7		T12	4		T10	7
all_values[13]	272	1			T1	7		T12	4		T10	7
all_values[14]	272	1			T1	7		T12	4		T10	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2274

1

T1

55

T12

30

T10

52

auto[1]

1806

1

T1

50

T12

30

T10

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

688

1

T1

16

T12

18

T10

8

auto[1]

3392

1

T1

89

T12

42

T10

97

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2378

1

T1

60

T12

38

T10

50

auto[1]

1702

1

T1

45

T12

22

T10

55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1			T12	1		T11	1		T38	4
all_values[0]	auto[0]	auto[0]	auto[1]	41	1			T1	2		T10	2		T11	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T1	2		T12	3		T28	1
all_values[0]	auto[0]	auto[1]	auto[1]	59	1			T10	2		T11	1		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	58	1			T1	3		T10	2		T11	1
all_values[0]	auto[1]	auto[1]	auto[1]	56	1			T10	1		T13	2		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	19	1			T12	1		T28	1		T39	2
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T1	3		T12	1		T10	2
all_values[1]	auto[0]	auto[1]	auto[0]	14	1			T12	1		T11	1		T38	2
all_values[1]	auto[0]	auto[1]	auto[1]	49	1			T10	1		T28	3		T29	3
all_values[1]	auto[1]	auto[0]	auto[1]	73	1			T12	1		T10	2		T13	3
all_values[1]	auto[1]	auto[1]	auto[1]	38	1			T1	4		T10	2		T11	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T1	5		T28	2		T71	2
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T12	1		T11	1		T28	2
all_values[2]	auto[0]	auto[1]	auto[0]	19	1			T1	2		T13	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1			T12	1		T10	3		T13	2
all_values[2]	auto[1]	auto[0]	auto[1]	62	1			T12	2		T10	1		T11	3
all_values[2]	auto[1]	auto[1]	auto[1]	54	1			T10	3		T28	2		T29	2
all_values[3]	auto[0]	auto[0]	auto[0]	25	1			T1	1		T11	2		T38	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1			T1	3		T12	2		T10	1
all_values[3]	auto[0]	auto[1]	auto[0]	11	1			T39	1		T72	2		T73	1
all_values[3]	auto[0]	auto[1]	auto[1]	48	1			T11	1		T13	3		T38	1
all_values[3]	auto[1]	auto[0]	auto[1]	74	1			T1	2		T10	4		T11	1
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T1	1		T12	2		T10	2
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T12	1		T29	1		T39	1
all_values[4]	auto[0]	auto[0]	auto[1]	53	1			T1	3		T12	1		T10	1
all_values[4]	auto[0]	auto[1]	auto[0]	17	1			T12	1		T13	1		T38	2
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T1	3		T10	2		T11	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1			T12	1		T10	4		T11	3
all_values[4]	auto[1]	auto[1]	auto[1]	45	1			T1	1		T28	4		T38	1
all_values[5]	auto[0]	auto[0]	auto[0]	27	1			T29	1		T71	3		T74	2
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T1	3		T12	1		T10	3
all_values[5]	auto[0]	auto[1]	auto[0]	15	1			T12	1		T13	1		T28	1
all_values[5]	auto[0]	auto[1]	auto[1]	47	1			T1	2		T10	1		T28	3
all_values[5]	auto[1]	auto[0]	auto[1]	58	1			T1	1		T12	1		T10	1
all_values[5]	auto[1]	auto[1]	auto[1]	56	1			T1	1		T12	1		T10	2
all_values[6]	auto[0]	auto[0]	auto[0]	27	1			T1	1		T10	1		T29	2
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T1	1		T13	2		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	16	1			T47	3		T74	1		T75	1
all_values[6]	auto[0]	auto[1]	auto[1]	58	1			T1	1		T12	1		T10	3
all_values[6]	auto[1]	auto[0]	auto[1]	62	1			T1	2		T12	2		T10	1
all_values[6]	auto[1]	auto[1]	auto[1]	46	1			T1	2		T12	1		T10	2
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T12	2		T10	2		T28	1
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T1	1		T12	1		T11	1
all_values[7]	auto[0]	auto[1]	auto[0]	12	1			T38	1		T71	1		T47	3
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T1	2		T10	1		T11	1
all_values[7]	auto[1]	auto[0]	auto[1]	61	1			T1	1		T12	1		T10	2
all_values[7]	auto[1]	auto[1]	auto[1]	51	1			T1	3		T10	2		T11	1
all_values[8]	auto[0]	auto[0]	auto[0]	21	1			T71	1		T47	2		T76	1
all_values[8]	auto[0]	auto[0]	auto[1]	54	1			T1	3		T11	2		T13	2
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T38	4		T39	2		T72	2
all_values[8]	auto[0]	auto[1]	auto[1]	60	1			T12	2		T10	3		T13	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1			T1	2		T12	1		T10	1
all_values[8]	auto[1]	auto[1]	auto[1]	50	1			T1	2		T12	1		T10	3
all_values[9]	auto[0]	auto[0]	auto[0]	24	1			T12	1		T10	1		T39	1
all_values[9]	auto[0]	auto[0]	auto[1]	54	1			T12	2		T11	1		T28	3
all_values[9]	auto[0]	auto[1]	auto[0]	11	1			T10	1		T28	1		T39	3
all_values[9]	auto[0]	auto[1]	auto[1]	61	1			T1	2		T10	3		T11	1
all_values[9]	auto[1]	auto[0]	auto[1]	73	1			T1	1		T11	2		T28	1
all_values[9]	auto[1]	auto[1]	auto[1]	49	1			T1	4		T12	1		T10	2
all_values[10]	auto[0]	auto[0]	auto[0]	23	1			T38	1		T71	2		T76	4
all_values[10]	auto[0]	auto[0]	auto[1]	64	1			T1	1		T10	2		T28	2
all_values[10]	auto[0]	auto[1]	auto[0]	8	1			T39	1		T48	1		T76	1
all_values[10]	auto[0]	auto[1]	auto[1]	60	1			T1	2		T12	2		T10	1
all_values[10]	auto[1]	auto[0]	auto[1]	49	1			T10	3		T13	1		T28	3
all_values[10]	auto[1]	auto[1]	auto[1]	68	1			T1	4		T12	2		T10	1
all_values[11]	auto[0]	auto[0]	auto[0]	43	1			T10	1		T11	2		T13	1
all_values[11]	auto[0]	auto[0]	auto[1]	46	1			T1	1		T12	2		T10	3
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T1	1		T13	1		T28	2
all_values[11]	auto[0]	auto[1]	auto[1]	55	1			T1	4		T11	1		T29	2
all_values[11]	auto[1]	auto[0]	auto[1]	62	1			T12	1		T10	2		T13	1
all_values[11]	auto[1]	auto[1]	auto[1]	37	1			T1	1		T12	1		T10	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1			T13	1		T29	4		T38	4
all_values[12]	auto[0]	auto[0]	auto[1]	62	1			T1	2		T10	2		T11	1
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T12	4		T28	1		T29	1
all_values[12]	auto[0]	auto[1]	auto[1]	57	1			T1	1		T10	1		T11	1
all_values[12]	auto[1]	auto[0]	auto[1]	64	1			T1	2		T10	1		T11	2
all_values[12]	auto[1]	auto[1]	auto[1]	43	1			T1	2		T10	3		T13	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T28	2		T29	1		T71	4
all_values[13]	auto[0]	auto[0]	auto[1]	55	1			T1	3		T12	1		T10	2
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T12	2		T13	2		T29	3
all_values[13]	auto[0]	auto[1]	auto[1]	48	1			T10	1		T11	1		T13	1
all_values[13]	auto[1]	auto[0]	auto[1]	65	1			T1	3		T12	1		T10	2
all_values[13]	auto[1]	auto[1]	auto[1]	49	1			T1	1		T10	2		T11	1
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T1	3		T10	1		T11	2
all_values[14]	auto[0]	auto[0]	auto[1]	58	1			T1	1		T12	1		T10	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1			T1	1		T10	1		T29	2
all_values[14]	auto[0]	auto[1]	auto[1]	54	1			T12	1		T10	1		T11	1
all_values[14]	auto[1]	auto[0]	auto[1]	63	1			T1	1		T10	1		T11	1
all_values[14]	auto[1]	auto[1]	auto[1]	44	1			T1	1		T12	2		T10	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal