Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.58 97.74 79.23 93.33 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core 92.58 97.74 79.23 93.33 100.00



Module Instance : tb.dut.i2c_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.58 97.74 79.23 93.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.46 95.94 84.08 71.43 91.18 94.69


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.48 100.00 100.00 93.91 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
intr_hw_acq_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_acq_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_cmd_complete 100.00 100.00 100.00 100.00 100.00
intr_hw_controller_halt 100.00 100.00 100.00 100.00 100.00
intr_hw_fmt_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_host_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_scl_interference 100.00 100.00 100.00 100.00 100.00
intr_hw_sda_interference 100.00 100.00 100.00 100.00 100.00
intr_hw_sda_unstable 100.00 100.00 100.00 100.00 100.00
intr_hw_stretch_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_stretch 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_unexp_stop 100.00 100.00 100.00 100.00 100.00
u_fifos 94.30 99.86 85.20 98.65 93.48
u_i2c_bus_monitor 89.23 96.26 89.25 81.82 89.58
u_i2c_controller_fsm 83.30 89.66 74.09 68.63 84.15 100.00
u_i2c_sync_scl 100.00 100.00 100.00
u_i2c_sync_sda 100.00 100.00 100.00
u_i2c_target_fsm 85.47 93.24 80.00 71.70 82.42 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_core
Line No.TotalCoveredPercent
TOTAL13313097.74
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22611100.00
CONT_ASSIGN22711100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24511100.00
CONT_ASSIGN24611100.00
CONT_ASSIGN24711100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25811100.00
ALWAYS26255100.00
ALWAYS27455100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN31111100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31411100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN36011100.00
CONT_ASSIGN36111100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN364100.00
CONT_ASSIGN365100.00
CONT_ASSIGN366100.00
CONT_ASSIGN36711100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN45511100.00
CONT_ASSIGN45611100.00
ALWAYS45955100.00
ALWAYS46966100.00
CONT_ASSIGN48511100.00
CONT_ASSIGN48611100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN85011100.00
CONT_ASSIGN85211100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN85711100.00
CONT_ASSIGN86511100.00
CONT_ASSIGN86811100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN87111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
237 1 1
238 1 1
240 1 1
242 1 1
243 1 1
245 1 1
246 1 1
247 1 1
249 1 1
253 1 1
255 1 1
256 1 1
257 1 1
258 1 1
262 1 1
263 1 1
264 1 1
267 1 1
268 1 1
274 1 1
275 1 1
276 1 1
278 1 1
279 1 1
283 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
306 1 1
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
313 1 1
314 1 1
317 1 1
319 1 1
321 1 1
323 1 1
325 1 1
326 1 1
331 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
344 1 1
345 1 1
346 1 1
347 1 1
348 1 1
349 1 1
358 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 0 1
365 0 1
366 0 1
367 1 1
368 1 1
412 1 1
417 1 1
419 1 1
422 1 1
423 1 1
428 1 1
455 1 1
456 1 1
459 1 1
460 1 1
461 1 1
463 1 1
464 1 1
469 1 1
470 1 1
471 1 1
480 1 1
481 1 1
482 1 1
MISSING_ELSE
485 1 1
486 1 1
488 1 1
489 1 1
491 1 1
850 1 1
852 1 1
854 1 1
856 1 1
857 1 1
865 1 1
868 1 1
870 1 1
871 1 1


Cond Coverage for Module : i2c_core
TotalCoveredPercent
Conditions13010379.23
Logical13010379.23
Non-Logical00
Event00

 LINE       237
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T10,T51

 LINE       242
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T93,T94

 LINE       243
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T93,T94

 LINE       249
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT6,T9,T13

 LINE       253
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11Not Covered

 LINE       267
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT6,T9,T13
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       268
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT6,T9,T13
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       294
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
             ------------1-----------    -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       294
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
                -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       296
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
             ------------1-----------    -----------------------2----------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11Not Covered

 LINE       296
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       303
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T47,T48
11Not Covered

 LINE       306
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT47,T95,T96
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       307
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------
-1--2-StatusTests
01CoveredT47,T95,T96
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       311
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT9,T96,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       312
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------
-1--2-StatusTests
01CoveredT9,T47,T95
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       325
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T9,T14
11CoveredT9,T11,T97

 LINE       326
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T47,T48
10CoveredT4,T10,T52

 LINE       331
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------
-1--2--3--4--5--6-StatusTests
011111Not Covered
101111Not Covered
110111Not Covered
111011Not Covered
111101Not Covered
111110Not Covered
111111CoveredT6,T9,T13

 LINE       344
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       345
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       346
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       347
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       348
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       349
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T13

 LINE       419
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       419
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       422
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       422
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       423
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       428
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T3,T4

 LINE       428
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T3,T4

 LINE       428
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       428
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT47,T98,T99
10CoveredT1,T2,T3

 LINE       428
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       455
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT6,T9,T13
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       456
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT6,T9,T13
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       471
 EXPRESSION ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q))
             -----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4

 LINE       471
 SUB-EXPRESSION (scl_fsm != scl_fsm_q)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       471
 SUB-EXPRESSION (sda_fsm != sda_fsm_q)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       481
 EXPRESSION (bus_event_detect_cnt != '0)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       485
 EXPRESSION (bus_event_detect_cnt == '0)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       486
 EXPRESSION (bus_event_detect && scl_sync && (sda_fsm_q != sda_sync))
             --------1-------    ----2---    -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T3,T4
110CoveredT1,T3,T4
111CoveredT1,T2,T3

 LINE       486
 SUB-EXPRESSION (sda_fsm_q != sda_sync)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       488
 EXPRESSION (controller_transmitting && sda_released_but_low)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T9,T13
11CoveredT12,T18,T19

 LINE       489
 EXPRESSION (target_transmitting && sda_released_but_low)
             ---------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11Not Covered

 LINE       854
 EXPRESSION (event_bus_active_timeout && ((!host_idle)))
             ------------1-----------    -------2------
-1--2-StatusTests
01CoveredT6,T9,T13
10Not Covered
11Not Covered

 LINE       865
 EXPRESSION (event_read_cmd_received && reg2hw.ctrl.tx_stretch_ctrl_en.q)
             -----------1-----------    ----------------2---------------
-1--2-StatusTests
01CoveredT3,T53,T54
10CoveredT1,T5,T44
11CoveredT3,T53,T54

Branch Coverage for Module : i2c_core
Line No.TotalCoveredPercent
Branches 30 28 93.33
TERNARY 242 2 2 100.00
TERNARY 243 2 2 100.00
TERNARY 344 2 2 100.00
TERNARY 345 2 2 100.00
TERNARY 346 2 2 100.00
TERNARY 347 2 2 100.00
TERNARY 348 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 422 2 1 50.00
TERNARY 423 2 1 50.00
IF 262 2 2 100.00
IF 274 2 2 100.00
IF 459 2 2 100.00
IF 469 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 242 (override) ?

Branches:
-1-StatusTests
1 Covered T2,T93,T94
0 Covered T1,T2,T3


LineNo. Expression -1-: 243 (override) ?

Branches:
-1-StatusTests
1 Covered T2,T93,T94
0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 345 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 346 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 348 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 422 (target_loopback) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 423 (target_loopback) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 274 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 459 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 469 if ((!rst_ni)) -2-: 471 if (((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q))) -3-: 481 if ((bus_event_detect_cnt != '0))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : i2c_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqFifoDepthValid_A 1375 1375 0 0
FifoDepthValid_A 1375 1375 0 0


AcqFifoDepthValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1375 1375 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FifoDepthValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1375 1375 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%