Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.48 100.00 100.00 93.91 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.28 97.06 89.50 97.22 71.43 94.04 98.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 87.46 95.94 84.08 71.43 91.18 94.69
i2c_csr_assert 93.75 93.75
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 98.60 98.59 96.81 100.00 97.58 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
132 1 1
133 1 1


Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT45,T177,T190
10CoveredT1,T2,T3
11CoveredT8,T45,T177

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 51 45 88.24
Total Bits 394 370 93.91
Total Bits 0->1 197 185 93.91
Total Bits 1->0 197 185 93.91

Ports 51 45 88.24
Port Bits 394 370 93.91
Port Bits 0->1 197 185 93.91
Port Bits 1->0 197 185 93.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T9,T11,T12 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T127,T191,T192 Yes T127,T191,T192 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T8,T45,T177 Yes T8,T45,T177 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T8,T45,T177 Yes T8,T45,T177 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T4,T6,T9 Yes T1,T3,T4 OUTPUT
intr_rx_threshold_o Yes Yes T9,T14,T40 Yes T9,T14,T40 OUTPUT
intr_acq_threshold_o Yes Yes T3,T7,T46 Yes T3,T7,T46 OUTPUT
intr_rx_overflow_o Yes Yes T9,T11,T29 Yes T9,T11,T29 OUTPUT
intr_controller_halt_o Yes Yes T12,T18,T19 Yes T12,T18,T19 OUTPUT
intr_scl_interference_o Yes Yes T18,T19,T20 Yes T18,T19,T20 OUTPUT
intr_sda_interference_o Yes Yes T12,T18,T19 Yes T12,T18,T19 OUTPUT
intr_stretch_timeout_o Yes Yes T6,T9,T14 Yes T6,T9,T14 OUTPUT
intr_sda_unstable_o Yes Yes T18,T19,T20 Yes T18,T19,T20 OUTPUT
intr_cmd_complete_o Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
intr_tx_stretch_o Yes Yes T1,T3,T5 Yes T1,T3,T5 OUTPUT
intr_tx_threshold_o Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
intr_acq_stretch_o Yes Yes T1,T4,T52 Yes T1,T4,T10 OUTPUT
intr_unexp_stop_o Yes Yes T29,T49,T50 Yes T29,T49,T50 OUTPUT
intr_host_timeout_o Yes Yes T67,T48,T75 Yes T67,T48,T75 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 230906174 230770626 0 0
CioSclEnKnownO_A 230906174 230770626 0 0
CioSclKnownO_A 230906174 230770626 0 0
CioSdaEnKnownO_A 230906174 230770626 0 0
CioSdaKnownO_A 230906174 230770626 0 0
FpvSecCmRegWeOnehotCheck_A 230906174 80 0 0
IntrAcqStretchKnownO_A 230906174 230770626 0 0
IntrAcqWtmkKnownO_A 230906174 230770626 0 0
IntrCommandCompleteKnownO_A 230906174 230770626 0 0
IntrControllerHaltKnownO_A 230906174 230770626 0 0
IntrFmtWtmkKnownO_A 230906174 230770626 0 0
IntrHostTimeoutKnownO_A 230906174 230770626 0 0
IntrRxOflwKnownO_A 230906174 230770626 0 0
IntrRxWtmkKnownO_A 230906174 230770626 0 0
IntrSclInterfKnownO_A 230906174 230770626 0 0
IntrSdaInterfKnownO_A 230906174 230770626 0 0
IntrSdaUnstableKnownO_A 230906174 230770626 0 0
IntrStretchTimeoutKnownO_A 230906174 230770626 0 0
IntrTxStretchKnownO_A 230906174 230770626 0 0
IntrTxWtmkKnownO_A 230906174 230770626 0 0
IntrUnexpStopKnownO_A 230906174 230770626 0 0
TlAReadyKnownO_A 230906174 230770626 0 0
TlDValidKnownO_A 230906174 230770626 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 80 0 0
T19 6388 0 0 0
T167 53160 0 0 0
T168 54377 0 0 0
T193 5591 20 0 0
T194 0 10 0 0
T195 0 20 0 0
T196 0 20 0 0
T197 0 10 0 0
T198 9969 0 0 0
T199 34729 0 0 0
T200 42557 0 0 0
T201 81769 0 0 0
T202 37199 0 0 0
T203 90859 0 0 0

IntrAcqStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230906174 230770626 0 0
T1 118607 118507 0 0
T2 2791 2731 0 0
T3 16343 16245 0 0
T4 46785 46717 0 0
T5 38917 38834 0 0
T6 62643 62583 0 0
T7 759396 759327 0 0
T8 939 855 0 0
T9 254616 254418 0 0
T10 44447 44359 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%