Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	231564133	0	0	0
ctrl_rd_A	231564133	2341	0	0
host_fifo_config_rd_A	231564133	3825	0	0
host_nack_handler_timeout_rd_A	231564133	1489	0	0
host_timeout_ctrl_rd_A	231564133	1404	0	0
intr_enable_rd_A	231564133	4457	0	0
ovrd_rd_A	231564133	2397	0	0
target_fifo_config_rd_A	231564133	1617	0	0
target_id_rd_A	231564133	2023	0	0
target_timeout_ctrl_rd_A	231564133	1693	0	0
timeout_ctrl_rd_A	231564133	1840	0	0
timing0_rd_A	231564133	1560	0	0
timing1_rd_A	231564133	1668	0	0
timing2_rd_A	231564133	1653	0	0
timing3_rd_A	231564133	1596	0	0
timing4_rd_A	231564133	1608	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	2341	0	0
T100	1674	1	0	0
T101	10522	201	0	0
T102	2762	7	0	0
T103	6947	29	0	0
T104	2336	1	0	0
T105	1183	9	0	0
T106	6979	97	0	0
T107	2265	2	0	0
T108	5794	7	0	0
T109	15283	223	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	3825	0	0
T29	0	137	0	0
T86	0	136	0	0
T110	375982	172	0	0
T111	0	174	0	0
T112	0	196	0	0
T113	0	142	0	0
T114	0	140	0	0
T115	0	248	0	0
T116	0	103	0	0
T117	0	209	0	0
T118	60341	0	0	0
T119	430640	0	0	0
T120	11516	0	0	0
T121	1639	0	0	0
T122	8885	0	0	0
T123	8738	0	0	0
T124	100273	0	0	0
T125	164741	0	0	0
T126	14640	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1489	0	0
T100	1674	2	0	0
T101	10522	194	0	0
T102	2762	8	0	0
T103	6947	60	0	0
T104	2336	6	0	0
T105	1183	1	0	0
T106	6979	50	0	0
T107	2265	1	0	0
T127	5599	17	0	0
T128	9551	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1404	0	0
T100	1674	4	0	0
T101	10522	197	0	0
T103	6947	26	0	0
T104	2336	3	0	0
T105	1183	8	0	0
T106	6979	30	0	0
T108	5794	24	0	0
T127	5599	13	0	0
T128	9551	6	0	0
T129	2204	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	4457	0	0
T29	107334	13	0	0
T100	0	9	0	0
T101	0	204	0	0
T102	0	10	0	0
T103	0	44	0	0
T104	0	28	0	0
T105	0	8	0	0
T127	0	41	0	0
T130	0	11	0	0
T131	0	9	0	0
T132	48395	0	0	0
T133	152582	0	0	0
T134	131494	0	0	0
T135	157479	0	0	0
T136	9930	0	0	0
T137	25413	0	0	0
T138	2042	0	0	0
T139	152699	0	0	0
T140	16120	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	2397	0	0
T2	2791	50	0	0
T3	16343	0	0	0
T4	46785	0	0	0
T5	38917	0	0	0
T6	62643	0	0	0
T7	759396	0	0	0
T8	939	0	0	0
T9	254616	0	0	0
T10	44447	0	0	0
T13	25209	0	0	0
T76	0	63	0	0
T141	0	58	0	0
T142	0	41	0	0
T143	0	36	0	0
T144	0	47	0	0
T145	0	43	0	0
T146	0	80	0	0
T147	0	76	0	0
T148	0	32	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1617	0	0
T100	1674	5	0	0
T101	10522	216	0	0
T102	2762	10	0	0
T103	6947	35	0	0
T105	1183	6	0	0
T106	6979	45	0	0
T107	2265	9	0	0
T108	5794	16	0	0
T128	9551	36	0	0
T129	2204	8	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	2023	0	0
T100	1674	9	0	0
T101	10522	200	0	0
T102	2762	21	0	0
T103	6947	28	0	0
T104	2336	9	0	0
T105	1183	4	0	0
T106	6979	167	0	0
T107	2265	26	0	0
T127	5599	7	0	0
T129	2204	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1693	0	0
T101	10522	249	0	0
T103	6947	94	0	0
T104	2336	4	0	0
T105	1183	4	0	0
T106	6979	62	0	0
T107	2265	5	0	0
T108	5794	8	0	0
T127	5599	6	0	0
T128	9551	14	0	0
T129	2204	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1840	0	0
T100	1674	6	0	0
T101	10522	209	0	0
T102	2762	23	0	0
T103	6947	53	0	0
T105	1183	7	0	0
T106	6979	71	0	0
T108	5794	13	0	0
T127	5599	8	0	0
T128	9551	18	0	0
T149	6742	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1560	0	0
T100	1674	2	0	0
T101	10522	193	0	0
T103	6947	38	0	0
T104	2336	1	0	0
T106	6979	49	0	0
T107	2265	5	0	0
T108	5794	15	0	0
T127	5599	10	0	0
T128	9551	17	0	0
T129	2204	15	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1668	0	0
T100	1674	7	0	0
T101	10522	177	0	0
T102	2762	36	0	0
T103	6947	74	0	0
T104	2336	10	0	0
T105	1183	2	0	0
T106	6979	71	0	0
T107	2265	20	0	0
T127	5599	8	0	0
T129	2204	14	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1653	0	0
T101	10522	188	0	0
T102	2762	15	0	0
T103	6947	38	0	0
T104	2336	6	0	0
T105	1183	7	0	0
T106	6979	43	0	0
T108	5794	12	0	0
T127	5599	32	0	0
T128	9551	29	0	0
T129	2204	2	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1596	0	0
T100	1674	6	0	0
T101	10522	189	0	0
T102	2762	17	0	0
T103	6947	63	0	0
T104	2336	10	0	0
T105	1183	3	0	0
T106	6979	66	0	0
T107	2265	1	0	0
T127	5599	10	0	0
T129	2204	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231564133	1608	0	0
T100	1674	7	0	0
T101	10522	211	0	0
T102	2762	14	0	0
T103	6947	38	0	0
T104	2336	9	0	0
T105	1183	3	0	0
T106	6979	68	0	0
T107	2265	8	0	0
T128	9551	14	0	0
T129	2204	6	0	0