Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.48	100.00	100.00	93.91			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	100.00	93.91			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.47	97.21	89.65	97.22	72.02	94.26	98.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	87.70	96.20	84.01		72.02	91.56	94.69
i2c_csr_assert	93.75						93.75
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	98.69	98.59	97.25	100.00		97.58	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
132	1	1
133	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T179
1	0	Covered	T1,T2,T3
1	1	Covered	T138,T177,T178

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	51	45	88.24
Total Bits	394	370	93.91
Total Bits 0->1	197	185	93.91
Total Bits 1->0	197	185	93.91

Ports	51	45	88.24
Port Bits	394	370	93.91
Port Bits 0->1	197	185	93.91
Port Bits 1->0	197	185	93.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T18,T19,T11	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T10	Yes	T1,T5,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T64,T180,T181	Yes	T64,T180,T181	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T138,T177,T178	Yes	T138,T177,T178	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T138,T177,T178	Yes	T138,T177,T178	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T2,T4,T7	Yes	T1,T2,T4	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T7,T10,T14	Yes	T2,T3,T4	OUTPUT
intr_rx_threshold_o	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
intr_acq_threshold_o	Yes	Yes	T6,T8,T57	Yes	T6,T8,T57	OUTPUT
intr_rx_overflow_o	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
intr_controller_halt_o	Yes	Yes	T24,T18,T25	Yes	T24,T18,T25	OUTPUT
intr_scl_interference_o	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
intr_sda_interference_o	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T2,T7,T10	Yes	T2,T7,T10	OUTPUT
intr_sda_unstable_o	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	OUTPUT
intr_cmd_complete_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_tx_stretch_o	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
intr_tx_threshold_o	Yes	Yes	T3,T4,T8	Yes	T2,T3,T4	OUTPUT
intr_acq_stretch_o	Yes	Yes	T9,T45,T46	Yes	T9,T45,T46	OUTPUT
intr_unexp_stop_o	Yes	Yes	T175,T107,T50	Yes	T175,T107,T50	OUTPUT
intr_host_timeout_o	Yes	Yes	T45,T68,T56	Yes	T45,T68,T56	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	363684497	363512641	0	0
CioSclEnKnownO_A	363684497	363512641	0	0
CioSclKnownO_A	363684497	363512641	0	0
CioSdaEnKnownO_A	363684497	363512641	0	0
CioSdaKnownO_A	363684497	363512641	0	0
FpvSecCmRegWeOnehotCheck_A	363684497	90	0	0
IntrAcqStretchKnownO_A	363684497	363512641	0	0
IntrAcqWtmkKnownO_A	363684497	363512641	0	0
IntrCommandCompleteKnownO_A	363684497	363512641	0	0
IntrControllerHaltKnownO_A	363684497	363512641	0	0
IntrFmtWtmkKnownO_A	363684497	363512641	0	0
IntrHostTimeoutKnownO_A	363684497	363512641	0	0
IntrRxOflwKnownO_A	363684497	363512641	0	0
IntrRxWtmkKnownO_A	363684497	363512641	0	0
IntrSclInterfKnownO_A	363684497	363512641	0	0
IntrSdaInterfKnownO_A	363684497	363512641	0	0
IntrSdaUnstableKnownO_A	363684497	363512641	0	0
IntrStretchTimeoutKnownO_A	363684497	363512641	0	0
IntrTxStretchKnownO_A	363684497	363512641	0	0
IntrTxWtmkKnownO_A	363684497	363512641	0	0
IntrUnexpStopKnownO_A	363684497	363512641	0	0
TlAReadyKnownO_A	363684497	363512641	0	0
TlDValidKnownO_A	363684497	363512641	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	90	0	0
T182	6832	20	0	0
T183	0	20	0	0
T184	0	20	0	0
T185	0	10	0	0
T186	0	20	0	0
T187	138342	0	0	0
T188	45760	0	0	0
T189	101491	0	0	0
T190	56789	0	0	0
T191	466769	0	0	0
T192	22339	0	0	0
T193	112296	0	0	0
T194	11318	0	0	0
T195	14063	0	0	0

IntrAcqStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrAcqWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrControllerHaltKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrTxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363684497	363512641	0	0
T1	10141	10067	0	0
T2	147248	147192	0	0
T3	12528	12443	0	0
T4	134614	134515	0	0
T5	8515	8450	0	0
T6	36732	36671	0	0
T7	207323	207234	0	0
T8	15497	15426	0	0
T9	82723	82634	0	0
T10	56136	56084	0	0