Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	364337875	0	0	0
ctrl_rd_A	364337875	2407	0	0
host_fifo_config_rd_A	364337875	3234	0	0
host_nack_handler_timeout_rd_A	364337875	1165	0	0
host_timeout_ctrl_rd_A	364337875	808	0	0
intr_enable_rd_A	364337875	4240	0	0
ovrd_rd_A	364337875	2061	0	0
target_fifo_config_rd_A	364337875	1224	0	0
target_id_rd_A	364337875	1649	0	0
target_timeout_ctrl_rd_A	364337875	1128	0	0
timeout_ctrl_rd_A	364337875	1458	0	0
timing0_rd_A	364337875	1196	0	0
timing1_rd_A	364337875	1080	0	0
timing2_rd_A	364337875	1152	0	0
timing3_rd_A	364337875	1054	0	0
timing4_rd_A	364337875	1145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	2407	0	0
T96	1872	30	0	0
T97	1379	31	0	0
T98	4148	2	0	0
T99	2566	37	0	0
T100	7446	98	0	0
T101	12306	17	0	0
T102	5859	39	0	0
T103	3564	65	0	0
T104	11878	50	0	0
T105	4066	4	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	3234	0	0
T15	656349	0	0	0
T38	12167	0	0	0
T45	143150	0	0	0
T62	126085	0	0	0
T68	118052	0	0	0
T70	10120	0	0	0
T71	11976	0	0	0
T76	410558	165	0	0
T77	322194	0	0	0
T93	2181	0	0	0
T106	0	65	0	0
T107	0	261	0	0
T108	0	216	0	0
T109	0	134	0	0
T110	0	107	0	0
T111	0	265	0	0
T112	0	200	0	0
T113	0	250	0	0
T114	0	95	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1165	0	0
T96	1872	19	0	0
T97	1379	7	0	0
T98	4148	2	0	0
T99	2566	12	0	0
T100	7446	38	0	0
T101	12306	1	0	0
T102	5859	11	0	0
T103	3564	31	0	0
T104	11878	34	0	0
T105	4066	3	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	808	0	0
T96	1872	6	0	0
T97	1379	7	0	0
T98	4148	9	0	0
T99	2566	9	0	0
T100	7446	7	0	0
T101	12306	19	0	0
T102	5859	1	0	0
T103	3564	13	0	0
T104	11878	45	0	0
T115	3129	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	4240	0	0
T96	0	5	0	0
T97	0	62	0	0
T98	0	5	0	0
T99	0	68	0	0
T100	0	77	0	0
T107	183322	11	0	0
T111	0	20	0	0
T116	0	23	0	0
T117	0	19	0	0
T118	0	27	0	0
T119	288380	0	0	0
T120	129249	0	0	0
T121	84876	0	0	0
T122	139783	0	0	0
T123	38787	0	0	0
T124	144071	0	0	0
T125	85840	0	0	0
T126	1275	0	0	0
T127	384259	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	2061	0	0
T48	11974	0	0	0
T49	14777	0	0	0
T74	0	49	0	0
T95	2395	31	0	0
T128	0	30	0	0
T129	0	42	0	0
T130	0	63	0	0
T131	0	32	0	0
T132	0	42	0	0
T133	0	52	0	0
T134	0	47	0	0
T135	0	51	0	0
T136	163366	0	0	0
T137	35085	0	0	0
T138	887	0	0	0
T139	2039	0	0	0
T140	15372	0	0	0
T141	197162	0	0	0
T142	12019	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1224	0	0
T96	1872	18	0	0
T99	2566	9	0	0
T100	7446	35	0	0
T101	12306	22	0	0
T102	5859	67	0	0
T103	3564	32	0	0
T104	11878	35	0	0
T115	3129	12	0	0
T143	6574	31	0	0
T144	13790	103	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1649	0	0
T96	1872	6	0	0
T97	1379	6	0	0
T99	2566	29	0	0
T100	7446	41	0	0
T101	12306	8	0	0
T102	5859	22	0	0
T103	3564	2	0	0
T104	11878	36	0	0
T105	4066	3	0	0
T115	3129	21	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1128	0	0
T96	1872	12	0	0
T97	1379	8	0	0
T98	4148	11	0	0
T99	2566	8	0	0
T100	7446	62	0	0
T101	12306	3	0	0
T102	5859	30	0	0
T103	3564	26	0	0
T104	11878	27	0	0
T115	3129	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1458	0	0
T96	1872	17	0	0
T97	1379	1	0	0
T99	2566	6	0	0
T100	7446	26	0	0
T101	12306	29	0	0
T102	5859	60	0	0
T103	3564	9	0	0
T104	11878	25	0	0
T105	4066	5	0	0
T115	3129	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1196	0	0
T96	1872	14	0	0
T97	1379	4	0	0
T99	2566	13	0	0
T100	7446	35	0	0
T101	12306	32	0	0
T102	5859	18	0	0
T103	3564	11	0	0
T104	11878	39	0	0
T105	4066	7	0	0
T115	3129	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1080	0	0
T96	1872	10	0	0
T97	1379	7	0	0
T99	2566	6	0	0
T100	7446	20	0	0
T101	12306	13	0	0
T102	5859	24	0	0
T103	3564	19	0	0
T104	11878	4	0	0
T115	3129	17	0	0
T143	6574	22	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1152	0	0
T96	1872	2	0	0
T97	1379	14	0	0
T98	4148	1	0	0
T99	2566	19	0	0
T100	7446	33	0	0
T101	12306	29	0	0
T102	5859	24	0	0
T103	3564	41	0	0
T104	11878	38	0	0
T105	4066	4	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1054	0	0
T96	1872	18	0	0
T97	1379	11	0	0
T98	4148	1	0	0
T99	2566	22	0	0
T100	7446	34	0	0
T101	12306	23	0	0
T102	5859	52	0	0
T103	3564	6	0	0
T104	11878	42	0	0
T143	6574	22	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364337875	1145	0	0
T96	1872	19	0	0
T98	4148	5	0	0
T99	2566	3	0	0
T100	7446	31	0	0
T101	12306	26	0	0
T102	5859	21	0	0
T103	3564	11	0	0
T104	11878	30	0	0
T105	4066	8	0	0
T143	6574	24	0	0