Summary for Variable cp_cmd_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_cmd_complete
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| complete |
39 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable cp_ip_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_ip_mode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| device |
37 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
| host |
2 |
1 |
|
|
T32 |
1 |
|
T76 |
1 |
|
- |
- |
Summary for Cross cp_read_x_complete
Samples crossed: cp_cmd_complete cp_ip_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
Automatically Generated Cross Bins for cp_read_x_complete
Uncovered bins
| cp_cmd_complete | cp_ip_mode | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
2 |
|
Summary for Cross cp_write_x_complete
Samples crossed: cp_cmd_complete cp_ip_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
Automatically Generated Cross Bins for cp_write_x_complete
Uncovered bins
| cp_cmd_complete | cp_ip_mode | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
2 |
|