Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24618	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

45015

1

T1

21

T2

58

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34232	1			T1	20		T2	71		T3	20
values[0x0]	17289	1			T1	7		T2	17		T3	11
values[0x1]	18112	1			T1	13		T2	29		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52432

1

T1

27

T2

78

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	219	1			T6	1		T13	1		T19	2
valid_sources[0x01]	228	1			T6	1		T7	1		T13	2
valid_sources[0x02]	225	1			T3	3		T6	2		T5	2
valid_sources[0x03]	264	1			T6	5		T7	1		T10	6
valid_sources[0x04]	176	1			T6	2		T13	3		T14	3
valid_sources[0x05]	267	1			T6	1		T9	12		T13	1
valid_sources[0x06]	209	1			T6	1		T7	1		T13	3
valid_sources[0x07]	192	1			T6	1		T23	7		T24	3
valid_sources[0x08]	214	1			T5	1		T10	8		T19	14
valid_sources[0x09]	332	1			T7	1		T10	14		T13	4
valid_sources[0x0a]	315	1			T5	2		T13	1		T19	3
valid_sources[0x0b]	265	1			T7	2		T13	1		T19	7
valid_sources[0x0c]	268	1			T6	2		T19	25		T14	2
valid_sources[0x0d]	239	1			T6	2		T5	1		T14	2
valid_sources[0x0e]	343	1			T10	1		T13	2		T19	27
valid_sources[0x0f]	223	1			T13	2		T19	5		T20	11
valid_sources[0x10]	236	1			T5	1		T13	1		T14	1
valid_sources[0x11]	245	1			T6	3		T5	1		T13	2
valid_sources[0x12]	234	1			T6	4		T7	1		T5	3
valid_sources[0x13]	250	1			T6	1		T7	1		T13	2
valid_sources[0x14]	185	1			T10	1		T19	1		T23	12
valid_sources[0x15]	226	1			T6	2		T5	2		T13	1
valid_sources[0x16]	205	1			T6	1		T7	1		T5	2
valid_sources[0x17]	208	1			T6	1		T5	1		T14	2
valid_sources[0x18]	254	1			T6	2		T7	1		T10	5
valid_sources[0x19]	206	1			T6	2		T13	2		T14	1
valid_sources[0x1a]	214	1			T6	2		T10	11		T13	4
valid_sources[0x1b]	196	1			T6	2		T13	1		T19	1
valid_sources[0x1c]	277	1			T6	1		T7	1		T19	1
valid_sources[0x1d]	342	1			T6	2		T7	1		T10	1
valid_sources[0x1e]	442	1			T6	2		T19	3		T14	1
valid_sources[0x1f]	311	1			T5	2		T9	1		T19	1
valid_sources[0x20]	226	1			T6	2		T7	1		T5	1
valid_sources[0x21]	280	1			T6	1		T4	55		T13	1
valid_sources[0x22]	261	1			T6	3		T13	1		T19	1
valid_sources[0x23]	234	1			T6	3		T7	1		T5	1
valid_sources[0x24]	262	1			T6	3		T10	9		T13	3
valid_sources[0x25]	280	1			T6	1		T5	2		T13	1
valid_sources[0x26]	217	1			T6	1		T10	5		T13	2
valid_sources[0x27]	204	1			T6	2		T13	1		T19	10
valid_sources[0x28]	244	1			T6	1		T13	1		T19	12
valid_sources[0x29]	307	1			T13	1		T19	11		T14	4
valid_sources[0x2a]	207	1			T6	1		T7	1		T13	1
valid_sources[0x2b]	293	1			T10	18		T13	4		T24	3
valid_sources[0x2c]	204	1			T6	2		T5	1		T19	17
valid_sources[0x2d]	336	1			T7	1		T29	3		T26	1
valid_sources[0x2e]	186	1			T6	2		T5	1		T20	1
valid_sources[0x2f]	256	1			T13	1		T14	1		T23	20
valid_sources[0x30]	257	1			T6	3		T19	10		T14	1
valid_sources[0x31]	279	1			T6	1		T5	1		T13	3
valid_sources[0x32]	278	1			T5	1		T10	1		T13	1
valid_sources[0x33]	397	1			T6	1		T7	1		T10	13
valid_sources[0x34]	393	1			T6	1		T13	1		T14	2
valid_sources[0x35]	361	1			T6	2		T7	1		T14	1
valid_sources[0x36]	356	1			T6	4		T10	3		T14	4
valid_sources[0x37]	271	1			T6	1		T4	12		T5	1
valid_sources[0x38]	212	1			T10	3		T19	2		T24	3
valid_sources[0x39]	184	1			T6	1		T10	2		T13	1
valid_sources[0x3a]	229	1			T5	2		T13	2		T19	21
valid_sources[0x3b]	395	1			T1	34		T6	5		T5	1
valid_sources[0x3c]	756	1			T6	1		T5	1		T10	1
valid_sources[0x3d]	199	1			T3	5		T6	2		T5	1
valid_sources[0x3e]	376	1			T6	1		T25	1		T29	5
valid_sources[0x3f]	319	1			T6	3		T7	1		T13	1
valid_sources[0x40]	246	1			T6	2		T5	1		T10	6
valid_sources[0x41]	267	1			T2	44		T7	1		T14	1
valid_sources[0x42]	195	1			T6	1		T10	4		T19	4
valid_sources[0x43]	339	1			T6	2		T7	2		T19	10
valid_sources[0x44]	295	1			T6	1		T10	1		T20	38
valid_sources[0x45]	242	1			T7	1		T13	5		T14	2
valid_sources[0x46]	187	1			T7	1		T13	2		T19	1
valid_sources[0x47]	320	1			T6	3		T7	2		T5	2
valid_sources[0x48]	211	1			T5	1		T10	5		T13	1
valid_sources[0x49]	566	1			T3	1		T6	1		T7	1
valid_sources[0x4a]	246	1			T3	1		T7	2		T5	1
valid_sources[0x4b]	375	1			T19	6		T14	5		T23	30
valid_sources[0x4c]	367	1			T6	2		T10	4		T13	3
valid_sources[0x4d]	254	1			T1	3		T6	4		T19	9
valid_sources[0x4e]	174	1			T13	2		T19	1		T25	1
valid_sources[0x4f]	214	1			T7	2		T5	1		T13	2
valid_sources[0x50]	204	1			T6	1		T5	1		T10	3
valid_sources[0x51]	286	1			T6	2		T8	39		T5	2
valid_sources[0x52]	419	1			T6	4		T5	1		T10	2
valid_sources[0x53]	253	1			T6	1		T7	3		T10	7
valid_sources[0x54]	356	1			T6	4		T13	2		T25	1
valid_sources[0x55]	273	1			T3	1		T7	1		T13	1
valid_sources[0x56]	233	1			T6	3		T7	3		T5	2
valid_sources[0x57]	224	1			T7	1		T5	1		T13	3
valid_sources[0x58]	316	1			T6	1		T5	1		T10	3
valid_sources[0x59]	530	1			T7	2		T5	1		T10	1
valid_sources[0x5a]	313	1			T6	2		T7	2		T10	1
valid_sources[0x5b]	211	1			T6	1		T13	2		T19	13
valid_sources[0x5c]	434	1			T2	12		T6	1		T7	1
valid_sources[0x5d]	263	1			T6	1		T19	5		T11	22
valid_sources[0x5e]	264	1			T6	2		T5	3		T10	1
valid_sources[0x5f]	201	1			T6	3		T13	2		T14	2
valid_sources[0x60]	236	1			T6	2		T7	1		T5	1
valid_sources[0x61]	279	1			T13	2		T20	14		T14	2
valid_sources[0x62]	247	1			T3	1		T6	1		T5	1
valid_sources[0x63]	237	1			T6	4		T13	1		T19	10
valid_sources[0x64]	231	1			T7	1		T10	7		T13	1
valid_sources[0x65]	332	1			T8	37		T5	1		T13	2
valid_sources[0x66]	308	1			T6	3		T10	4		T13	2
valid_sources[0x67]	382	1			T6	2		T14	2		T29	2
valid_sources[0x68]	327	1			T6	1		T7	2		T5	1
valid_sources[0x69]	261	1			T6	2		T7	1		T5	1
valid_sources[0x6a]	276	1			T6	3		T7	2		T13	1
valid_sources[0x6b]	264	1			T6	3		T7	1		T14	3
valid_sources[0x6c]	231	1			T6	2		T7	1		T5	1
valid_sources[0x6d]	234	1			T7	1		T13	1		T19	5
valid_sources[0x6e]	203	1			T6	4		T7	1		T5	1
valid_sources[0x6f]	175	1			T6	2		T5	1		T13	3
valid_sources[0x70]	245	1			T13	2		T14	6		T24	1
valid_sources[0x71]	269	1			T13	2		T14	2		T12	1
valid_sources[0x72]	213	1			T6	1		T13	3		T19	3
valid_sources[0x73]	176	1			T6	4		T5	2		T10	1
valid_sources[0x74]	190	1			T6	2		T5	2		T10	6
valid_sources[0x75]	276	1			T6	2		T5	1		T10	2
valid_sources[0x76]	234	1			T6	2		T7	1		T13	4
valid_sources[0x77]	214	1			T10	1		T13	3		T14	3
valid_sources[0x78]	282	1			T6	6		T13	3		T19	2
valid_sources[0x79]	405	1			T6	2		T7	1		T5	1
valid_sources[0x7a]	273	1			T7	2		T13	2		T24	2
valid_sources[0x7b]	441	1			T2	46		T3	7		T6	6
valid_sources[0x7c]	322	1			T6	3		T5	1		T13	2
valid_sources[0x7d]	365	1			T6	1		T5	1		T10	2
valid_sources[0x7e]	198	1			T7	2		T5	1		T10	16
valid_sources[0x7f]	410	1			T6	1		T7	1		T5	1
valid_sources[0x80]	349	1			T6	1		T7	1		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16009

1

T1

13

T2

24

T3

9

values[0x0]

all_enables

biggest_size

14886

1

T1

5

T2

14

T3

6

values[0x1]

all_enables

biggest_size

14120

1

T1

3

T2

20

T3

3