Module Definition
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Module Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.91 100.00 95.65 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.42 100.00 97.69 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 66.67
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataWidthCheck_A 330 330 0 0
PayLoadWidthCheck 330 330 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 330 330 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 330 330 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataWidthCheck_A 165 165 0 0
PayLoadWidthCheck 165 165 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 165 165 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 165 165 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataWidthCheck_A 165 165 0 0
PayLoadWidthCheck 165 165 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 165 165 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 165 165 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0