Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	646470	0	0	0
ctrl_rd_A	646470	2268	0	0
host_fifo_config_rd_A	646470	1350	0	0
host_nack_handler_timeout_rd_A	646470	1416	0	0
host_timeout_ctrl_rd_A	646470	1272	0	0
intr_enable_rd_A	646470	4032	0	0
ovrd_rd_A	646470	1585	0	0
target_fifo_config_rd_A	646470	1338	0	0
target_id_rd_A	646470	1691	0	0
target_timeout_ctrl_rd_A	646470	1344	0	0
timeout_ctrl_rd_A	646470	1464	0	0
timing0_rd_A	646470	1370	0	0
timing1_rd_A	646470	1475	0	0
timing2_rd_A	646470	1377	0	0
timing3_rd_A	646470	1386	0	0
timing4_rd_A	646470	1455	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	2268	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	22	0	0
T17	0	16	0	0
T20	6582	52	0	0
T23	4888	26	0	0
T24	3959	20	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	26	0	0
T29	2315	0	0	0
T41	0	53	0	0
T47	2780	0	0	0
T51	0	95	0	0
T52	0	76	0	0
T53	0	80	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1350	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	8	0	0
T17	0	12	0	0
T20	6582	51	0	0
T23	4888	5	0	0
T24	3959	34	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	12	0	0
T29	2315	0	0	0
T41	0	10	0	0
T47	2780	0	0	0
T51	0	64	0	0
T52	0	43	0	0
T53	0	17	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1416	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	29	0	0
T17	0	46	0	0
T20	6582	51	0	0
T23	4888	19	0	0
T24	3959	23	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	19	0	0
T29	2315	0	0	0
T41	0	13	0	0
T47	2780	0	0	0
T51	0	47	0	0
T52	0	23	0	0
T53	0	18	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1272	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	38	0	0
T17	0	48	0	0
T20	6582	95	0	0
T23	4888	11	0	0
T24	3959	0	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	3	0	0
T29	2315	0	0	0
T41	0	10	0	0
T47	2780	0	0	0
T51	0	39	0	0
T52	0	54	0	0
T53	0	12	0	0
T54	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	4032	0	0
T1	1613	5	0	0
T2	1299	0	0	0
T3	1056	0	0	0
T4	1137	0	0	0
T5	2204	0	0	0
T6	5851	0	0	0
T7	2387	0	0	0
T8	1159	0	0	0
T9	1611	0	0	0
T10	4225	0	0	0
T12	0	10	0	0
T14	0	25	0	0
T20	0	2	0	0
T23	0	12	0	0
T24	0	29	0	0
T28	0	104	0	0
T38	0	17	0	0
T40	0	23	0	0
T50	0	22	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1585	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	36	0	0
T17	0	22	0	0
T20	6582	19	0	0
T23	4888	14	0	0
T24	3959	19	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	30	0	0
T29	2315	0	0	0
T41	0	3	0	0
T47	2780	0	0	0
T51	0	79	0	0
T52	0	58	0	0
T53	0	34	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1338	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	19	0	0
T17	0	41	0	0
T20	6582	28	0	0
T23	4888	14	0	0
T24	3959	28	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	17	0	0
T29	2315	0	0	0
T41	0	8	0	0
T47	2780	0	0	0
T51	0	57	0	0
T52	0	37	0	0
T53	0	15	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1691	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	5	0	0
T17	0	19	0	0
T20	6582	2	0	0
T23	4888	73	0	0
T24	3959	15	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	31	0	0
T29	2315	0	0	0
T41	0	4	0	0
T47	2780	0	0	0
T51	0	90	0	0
T52	0	9	0	0
T53	0	25	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1344	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	23	0	0
T17	0	19	0	0
T20	6582	40	0	0
T23	4888	14	0	0
T24	3959	4	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	6	0	0
T29	2315	0	0	0
T41	0	4	0	0
T47	2780	0	0	0
T51	0	54	0	0
T52	0	20	0	0
T53	0	23	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1464	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	17	0	0
T17	0	32	0	0
T20	6582	32	0	0
T23	4888	15	0	0
T24	3959	20	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	8	0	0
T29	2315	0	0	0
T41	0	7	0	0
T47	2780	0	0	0
T51	0	87	0	0
T52	0	35	0	0
T53	0	22	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1370	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	26	0	0
T17	0	40	0	0
T20	6582	67	0	0
T23	4888	26	0	0
T24	3959	25	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	13	0	0
T29	2315	0	0	0
T41	0	5	0	0
T47	2780	0	0	0
T51	0	34	0	0
T52	0	39	0	0
T53	0	13	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1475	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	30	0	0
T17	0	29	0	0
T20	6582	56	0	0
T23	4888	19	0	0
T24	3959	18	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	10	0	0
T29	2315	0	0	0
T41	0	9	0	0
T47	2780	0	0	0
T51	0	45	0	0
T52	0	40	0	0
T53	0	26	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1377	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	15	0	0
T17	0	17	0	0
T20	6582	40	0	0
T23	4888	34	0	0
T24	3959	5	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	12	0	0
T29	2315	0	0	0
T41	0	2	0	0
T47	2780	0	0	0
T51	0	61	0	0
T52	0	12	0	0
T53	0	14	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1386	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	51	0	0
T17	0	24	0	0
T20	6582	44	0	0
T23	4888	30	0	0
T24	3959	18	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	2	0	0
T29	2315	0	0	0
T41	0	9	0	0
T47	2780	0	0	0
T51	0	85	0	0
T52	0	32	0	0
T53	0	21	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646470	1455	0	0
T11	1145	0	0	0
T12	1764	0	0	0
T14	11438	16	0	0
T17	0	20	0	0
T20	6582	47	0	0
T23	4888	0	0	0
T24	3959	7	0	0
T25	1648	0	0	0
T26	4428	0	0	0
T28	0	23	0	0
T29	2315	0	0	0
T41	0	10	0	0
T47	2780	0	0	0
T51	0	64	0	0
T52	0	46	0	0
T53	0	30	0	0
T54	0	13	0	0