Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42415

1

T1

562

T2

551

T3

556

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33524	1			T1	816		T2	229		T3	757
values[0x0]	16535	1			T1	301		T2	155		T3	305
values[0x1]	17419	1			T1	304		T2	167		T3	293

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50066

1

T1

860

T2

551

T3

840

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	191	1			T1	5		T2	1		T3	4
valid_sources[0x01]	314	1			T1	8		T2	1		T3	2
valid_sources[0x02]	345	1			T1	4		T2	4		T3	2
valid_sources[0x03]	218	1			T1	5		T2	3		T3	10
valid_sources[0x04]	285	1			T1	10		T2	3		T5	1
valid_sources[0x05]	328	1			T1	2		T2	9		T3	4
valid_sources[0x06]	312	1			T1	2		T3	6		T6	5
valid_sources[0x07]	451	1			T1	2		T3	8		T12	1
valid_sources[0x08]	130	1			T1	3		T3	7		T12	1
valid_sources[0x09]	204	1			T1	2		T3	6		T12	1
valid_sources[0x0a]	204	1			T1	4		T3	7		T5	1
valid_sources[0x0b]	316	1			T1	6		T3	17		T26	1
valid_sources[0x0c]	216	1			T1	8		T2	6		T3	7
valid_sources[0x0d]	271	1			T1	11		T2	7		T3	7
valid_sources[0x0e]	206	1			T1	4		T2	3		T3	7
valid_sources[0x0f]	181	1			T1	5		T2	4		T3	6
valid_sources[0x10]	307	1			T1	2		T3	10		T12	1
valid_sources[0x11]	251	1			T1	8		T2	3		T3	2
valid_sources[0x12]	220	1			T1	9		T2	1		T3	3
valid_sources[0x13]	256	1			T1	1		T3	5		T5	2
valid_sources[0x14]	229	1			T1	9		T2	4		T3	9
valid_sources[0x15]	290	1			T1	13		T2	10		T3	10
valid_sources[0x16]	299	1			T1	4		T3	10		T14	1
valid_sources[0x17]	394	1			T1	2		T3	2		T12	6
valid_sources[0x18]	496	1			T1	9		T2	2		T3	3
valid_sources[0x19]	152	1			T1	2		T3	2		T16	4
valid_sources[0x1a]	154	1			T1	6		T2	2		T3	10
valid_sources[0x1b]	342	1			T1	2		T3	4		T6	4
valid_sources[0x1c]	331	1			T1	1		T3	4		T6	12
valid_sources[0x1d]	261	1			T1	6		T3	1		T11	8
valid_sources[0x1e]	149	1			T1	6		T2	3		T3	2
valid_sources[0x1f]	172	1			T1	9		T3	3		T11	8
valid_sources[0x20]	229	1			T1	6		T2	5		T3	2
valid_sources[0x21]	232	1			T1	4		T3	10		T12	4
valid_sources[0x22]	316	1			T1	6		T2	2		T3	6
valid_sources[0x23]	417	1			T1	6		T2	12		T3	3
valid_sources[0x24]	353	1			T1	3		T3	6		T7	2
valid_sources[0x25]	242	1			T1	8		T3	8		T12	3
valid_sources[0x26]	245	1			T1	12		T2	1		T3	5
valid_sources[0x27]	214	1			T1	3		T3	9		T12	3
valid_sources[0x28]	224	1			T1	6		T3	3		T12	2
valid_sources[0x29]	244	1			T1	1		T2	2		T3	3
valid_sources[0x2a]	213	1			T1	3		T2	4		T3	7
valid_sources[0x2b]	155	1			T1	5		T2	2		T3	3
valid_sources[0x2c]	335	1			T1	2		T2	2		T3	1
valid_sources[0x2d]	233	1			T1	8		T2	4		T3	3
valid_sources[0x2e]	201	1			T1	4		T3	3		T12	2
valid_sources[0x2f]	175	1			T1	3		T12	10		T22	9
valid_sources[0x30]	156	1			T1	9		T2	1		T3	1
valid_sources[0x31]	249	1			T1	13		T2	7		T3	5
valid_sources[0x32]	185	1			T1	8		T3	1		T12	1
valid_sources[0x33]	155	1			T1	2		T3	3		T14	2
valid_sources[0x34]	264	1			T1	6		T3	14		T12	1
valid_sources[0x35]	271	1			T1	13		T2	6		T3	2
valid_sources[0x36]	309	1			T1	2		T3	3		T5	2
valid_sources[0x37]	264	1			T1	7		T2	11		T26	3
valid_sources[0x38]	295	1			T1	6		T2	5		T3	12
valid_sources[0x39]	225	1			T1	11		T3	7		T12	1
valid_sources[0x3a]	290	1			T1	15		T3	15		T16	5
valid_sources[0x3b]	185	1			T1	7		T2	2		T3	5
valid_sources[0x3c]	196	1			T1	4		T3	16		T12	4
valid_sources[0x3d]	217	1			T1	3		T2	5		T3	6
valid_sources[0x3e]	167	1			T1	5		T2	3		T5	1
valid_sources[0x3f]	270	1			T1	3		T3	2		T16	6
valid_sources[0x40]	180	1			T1	2		T2	4		T3	5
valid_sources[0x41]	254	1			T1	7		T2	1		T3	6
valid_sources[0x42]	265	1			T1	9		T3	2		T6	4
valid_sources[0x43]	269	1			T1	10		T2	21		T3	6
valid_sources[0x44]	307	1			T1	6		T2	9		T3	7
valid_sources[0x45]	249	1			T1	8		T2	9		T3	8
valid_sources[0x46]	360	1			T1	3		T3	9		T16	8
valid_sources[0x47]	192	1			T1	6		T2	2		T3	3
valid_sources[0x48]	232	1			T1	7		T2	3		T3	10
valid_sources[0x49]	274	1			T1	8		T2	2		T3	10
valid_sources[0x4a]	376	1			T1	9		T2	3		T3	7
valid_sources[0x4b]	346	1			T1	5		T2	2		T3	1
valid_sources[0x4c]	301	1			T1	4		T3	8		T12	4
valid_sources[0x4d]	248	1			T1	2		T3	11		T14	3
valid_sources[0x4e]	292	1			T1	5		T2	1		T3	9
valid_sources[0x4f]	186	1			T1	4		T3	1		T12	9
valid_sources[0x50]	204	1			T1	4		T2	1		T3	6
valid_sources[0x51]	215	1			T1	3		T14	3		T18	5
valid_sources[0x52]	224	1			T1	8		T3	1		T14	1
valid_sources[0x53]	204	1			T1	2		T2	3		T3	5
valid_sources[0x54]	212	1			T1	5		T3	12		T12	1
valid_sources[0x55]	314	1			T1	7		T3	3		T4	1
valid_sources[0x56]	183	1			T1	7		T3	2		T4	1
valid_sources[0x57]	175	1			T2	5		T3	5		T12	6
valid_sources[0x58]	377	1			T1	3		T2	8		T3	6
valid_sources[0x59]	203	1			T1	8		T2	4		T3	1
valid_sources[0x5a]	286	1			T1	3		T3	7		T6	24
valid_sources[0x5b]	221	1			T1	3		T2	1		T3	10
valid_sources[0x5c]	374	1			T1	7		T3	4		T12	1
valid_sources[0x5d]	376	1			T1	5		T2	1		T12	3
valid_sources[0x5e]	238	1			T1	3		T3	8		T12	3
valid_sources[0x5f]	263	1			T1	11		T3	10		T6	14
valid_sources[0x60]	338	1			T1	13		T2	5		T3	6
valid_sources[0x61]	285	1			T1	6		T3	5		T11	8
valid_sources[0x62]	281	1			T1	8		T3	3		T12	2
valid_sources[0x63]	333	1			T1	4		T2	7		T3	2
valid_sources[0x64]	302	1			T1	5		T3	5		T6	48
valid_sources[0x65]	255	1			T1	4		T2	5		T3	4
valid_sources[0x66]	355	1			T1	3		T2	1		T3	9
valid_sources[0x67]	513	1			T1	2		T3	3		T12	5
valid_sources[0x68]	218	1			T1	5		T3	3		T12	1
valid_sources[0x69]	344	1			T1	3		T3	4		T12	6
valid_sources[0x6a]	226	1			T1	5		T3	7		T12	3
valid_sources[0x6b]	237	1			T1	5		T3	1		T12	3
valid_sources[0x6c]	270	1			T1	4		T3	11		T4	1
valid_sources[0x6d]	314	1			T1	1		T2	5		T3	1
valid_sources[0x6e]	214	1			T1	7		T3	8		T12	1
valid_sources[0x6f]	221	1			T1	2		T2	3		T3	9
valid_sources[0x70]	227	1			T1	7		T2	7		T3	11
valid_sources[0x71]	351	1			T1	10		T2	3		T3	2
valid_sources[0x72]	309	1			T1	3		T3	5		T7	1
valid_sources[0x73]	263	1			T1	6		T22	6		T15	14
valid_sources[0x74]	433	1			T1	11		T2	1		T3	12
valid_sources[0x75]	212	1			T1	2		T2	9		T3	4
valid_sources[0x76]	198	1			T1	11		T2	2		T3	2
valid_sources[0x77]	232	1			T1	12		T12	7		T26	7
valid_sources[0x78]	189	1			T1	2		T3	2		T6	11
valid_sources[0x79]	360	1			T1	9		T2	3		T3	17
valid_sources[0x7a]	223	1			T1	1		T2	10		T3	18
valid_sources[0x7b]	330	1			T1	6		T5	1		T7	1
valid_sources[0x7c]	181	1			T1	3		T2	4		T3	4
valid_sources[0x7d]	314	1			T1	4		T3	2		T11	8
valid_sources[0x7e]	357	1			T1	5		T2	2		T3	4
valid_sources[0x7f]	300	1			T1	6		T2	11		T3	7
valid_sources[0x80]	465	1			T1	5		T2	2		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15009

1

T1

129

T2

229

T3

126

values[0x0]

all_enables

biggest_size

14021

1

T1

229

T2

155

T3

220

values[0x1]

all_enables

biggest_size

13385

1

T1

204

T2

167

T3

210