Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	651351	0	0	0
ctrl_rd_A	651351	1999	0	0
host_fifo_config_rd_A	651351	1450	0	0
host_nack_handler_timeout_rd_A	651351	1390	0	0
host_timeout_ctrl_rd_A	651351	1301	0	0
intr_enable_rd_A	651351	3064	0	0
ovrd_rd_A	651351	1640	0	0
target_fifo_config_rd_A	651351	1432	0	0
target_id_rd_A	651351	1433	0	0
target_timeout_ctrl_rd_A	651351	1416	0	0
timeout_ctrl_rd_A	651351	1485	0	0
timing0_rd_A	651351	1260	0	0
timing1_rd_A	651351	1463	0	0
timing2_rd_A	651351	1509	0	0
timing3_rd_A	651351	1330	0	0
timing4_rd_A	651351	1277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1999	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	6	0	0
T14	6502	1	0	0
T15	5962	8	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	32	0	0
T26	4248	0	0	0
T27	0	4	0	0
T29	0	26	0	0
T30	0	441	0	0
T31	0	106	0	0
T42	0	22	0	0
T44	0	8	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1450	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	33	0	0
T14	6502	13	0	0
T15	5962	25	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	24	0	0
T26	4248	0	0	0
T27	0	6	0	0
T29	0	6	0	0
T30	0	434	0	0
T31	0	100	0	0
T42	0	12	0	0
T44	0	17	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1390	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	35	0	0
T14	6502	8	0	0
T15	5962	8	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	8	0	0
T26	4248	0	0	0
T27	0	2	0	0
T29	0	14	0	0
T30	0	416	0	0
T31	0	101	0	0
T42	0	8	0	0
T44	0	8	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1301	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T14	6502	6	0	0
T15	5962	9	0	0
T16	3567	0	0	0
T17	2366	0	0	0
T18	10070	0	0	0
T23	6130	0	0	0
T24	0	20	0	0
T26	4248	0	0	0
T27	0	4	0	0
T29	0	7	0	0
T30	0	494	0	0
T31	0	92	0	0
T41	1079	0	0	0
T42	0	41	0	0
T44	0	15	0	0
T45	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	3064	0	0
T4	3188	0	0	0
T5	1897	8	0	0
T6	6877	0	0	0
T7	775	0	0	0
T9	0	24	0	0
T10	0	40	0	0
T11	1601	0	0	0
T12	2002	0	0	0
T13	4283	2	0	0
T14	6502	9	0	0
T15	0	4	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T24	0	19	0	0
T29	0	53	0	0
T30	0	426	0	0
T31	0	90	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1640	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	45	0	0
T14	6502	13	0	0
T15	5962	5	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	39	0	0
T26	4248	0	0	0
T27	0	15	0	0
T29	0	8	0	0
T30	0	443	0	0
T31	0	111	0	0
T42	0	36	0	0
T44	0	21	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1432	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	43	0	0
T14	6502	14	0	0
T15	5962	10	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	20	0	0
T26	4248	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T30	0	420	0	0
T31	0	109	0	0
T42	0	55	0	0
T44	0	38	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1433	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	16	0	0
T14	6502	4	0	0
T15	5962	1	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	13	0	0
T26	4248	0	0	0
T27	0	4	0	0
T29	0	27	0	0
T30	0	368	0	0
T31	0	78	0	0
T42	0	34	0	0
T44	0	19	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1416	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	2	0	0
T14	6502	5	0	0
T15	5962	0	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	22	0	0
T26	4248	0	0	0
T27	0	6	0	0
T29	0	9	0	0
T30	0	453	0	0
T31	0	106	0	0
T42	0	39	0	0
T44	0	7	0	0
T45	0	21	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1485	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	10	0	0
T14	6502	20	0	0
T15	5962	10	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	19	0	0
T26	4248	0	0	0
T27	0	5	0	0
T29	0	17	0	0
T30	0	442	0	0
T31	0	115	0	0
T42	0	17	0	0
T44	0	33	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1260	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	15	0	0
T14	6502	17	0	0
T15	5962	7	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	28	0	0
T26	4248	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T30	0	437	0	0
T31	0	111	0	0
T42	0	12	0	0
T44	0	26	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1463	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	24	0	0
T14	6502	18	0	0
T15	5962	19	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	25	0	0
T26	4248	0	0	0
T27	0	4	0	0
T29	0	18	0	0
T30	0	428	0	0
T31	0	120	0	0
T42	0	22	0	0
T44	0	15	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1509	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	66	0	0
T14	6502	3	0	0
T15	5962	10	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	12	0	0
T26	4248	0	0	0
T27	0	5	0	0
T29	0	12	0	0
T30	0	435	0	0
T31	0	89	0	0
T42	0	35	0	0
T44	0	14	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1330	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	10	0	0
T14	6502	3	0	0
T15	5962	4	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	8	0	0
T26	4248	0	0	0
T27	0	10	0	0
T29	0	7	0	0
T30	0	451	0	0
T31	0	113	0	0
T42	0	30	0	0
T44	0	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651351	1277	0	0
T8	1793	0	0	0
T9	1148	0	0	0
T13	4283	2	0	0
T14	6502	8	0	0
T15	5962	0	0	0
T16	3567	0	0	0
T21	2805	0	0	0
T22	1381	0	0	0
T23	6130	0	0	0
T24	0	7	0	0
T26	4248	0	0	0
T27	0	6	0	0
T29	0	6	0	0
T30	0	459	0	0
T31	0	114	0	0
T42	0	25	0	0
T44	0	16	0	0
T45	0	22	0	0