| T1559 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_override.3709578009 |
|
|
Aug 23 09:56:53 PM UTC 24 |
Aug 23 09:56:55 PM UTC 24 |
20129352 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.3773259195 |
|
|
Aug 23 09:56:55 PM UTC 24 |
Aug 23 09:56:57 PM UTC 24 |
101002436 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.1087727461 |
|
|
Aug 23 09:52:51 PM UTC 24 |
Aug 23 09:56:58 PM UTC 24 |
51156890573 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3288572093 |
|
|
Aug 23 09:56:56 PM UTC 24 |
Aug 23 09:57:02 PM UTC 24 |
1375628827 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.973856752 |
|
|
Aug 23 09:56:59 PM UTC 24 |
Aug 23 09:57:07 PM UTC 24 |
151147372 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1209952585 |
|
|
Aug 23 09:57:06 PM UTC 24 |
Aug 23 09:57:09 PM UTC 24 |
185010037 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.338720357 |
|
|
Aug 23 09:57:10 PM UTC 24 |
Aug 23 09:57:17 PM UTC 24 |
381625013 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.1150352220 |
|
|
Aug 23 09:56:53 PM UTC 24 |
Aug 23 09:57:26 PM UTC 24 |
1984638464 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1059717438 |
|
|
Aug 23 09:57:08 PM UTC 24 |
Aug 23 09:57:42 PM UTC 24 |
3619783731 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.4240823819 |
|
|
Aug 23 09:56:54 PM UTC 24 |
Aug 23 09:57:52 PM UTC 24 |
10646273180 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/43.i2c_host_perf.922304046 |
|
|
Aug 23 09:54:17 PM UTC 24 |
Aug 23 09:57:53 PM UTC 24 |
51435821417 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.1814703701 |
|
|
Aug 23 09:57:27 PM UTC 24 |
Aug 23 09:57:56 PM UTC 24 |
3402784565 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.1337509509 |
|
|
Aug 23 09:56:59 PM UTC 24 |
Aug 23 09:57:58 PM UTC 24 |
30434982323 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.670413373 |
|
|
Aug 23 09:57:57 PM UTC 24 |
Aug 23 09:58:02 PM UTC 24 |
2404999093 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.1543374369 |
|
|
Aug 23 09:57:53 PM UTC 24 |
Aug 23 09:58:08 PM UTC 24 |
1657334950 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.3735953085 |
|
|
Aug 23 09:58:02 PM UTC 24 |
Aug 23 09:58:09 PM UTC 24 |
5075697459 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.1202577157 |
|
|
Aug 23 09:57:53 PM UTC 24 |
Aug 23 09:58:10 PM UTC 24 |
4580372182 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1269181197 |
|
|
Aug 23 09:56:54 PM UTC 24 |
Aug 23 09:58:11 PM UTC 24 |
4553027294 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.1313193195 |
|
|
Aug 23 09:55:53 PM UTC 24 |
Aug 23 09:58:12 PM UTC 24 |
29239052132 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.2551007835 |
|
|
Aug 23 09:59:31 PM UTC 24 |
Aug 23 10:00:08 PM UTC 24 |
31042260007 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.848887855 |
|
|
Aug 23 09:58:10 PM UTC 24 |
Aug 23 09:58:13 PM UTC 24 |
277769625 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.269709932 |
|
|
Aug 23 09:58:10 PM UTC 24 |
Aug 23 09:58:13 PM UTC 24 |
185080466 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.1671332176 |
|
|
Aug 23 09:58:14 PM UTC 24 |
Aug 23 09:58:16 PM UTC 24 |
60614252 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1814347796 |
|
|
Aug 23 09:55:12 PM UTC 24 |
Aug 23 09:58:16 PM UTC 24 |
39175579730 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.191389800 |
|
|
Aug 23 09:58:14 PM UTC 24 |
Aug 23 09:58:19 PM UTC 24 |
2971744585 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2221019878 |
|
|
Aug 23 10:00:00 PM UTC 24 |
Aug 23 10:00:06 PM UTC 24 |
135484848 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.647357442 |
|
|
Aug 23 09:58:17 PM UTC 24 |
Aug 23 09:58:20 PM UTC 24 |
310680311 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_perf.3872972094 |
|
|
Aug 23 09:58:11 PM UTC 24 |
Aug 23 09:58:20 PM UTC 24 |
2078862501 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.132778340 |
|
|
Aug 23 09:58:20 PM UTC 24 |
Aug 23 09:58:22 PM UTC 24 |
607726109 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2563261045 |
|
|
Aug 23 09:58:21 PM UTC 24 |
Aug 23 09:58:24 PM UTC 24 |
556378701 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2819338007 |
|
|
Aug 23 09:58:21 PM UTC 24 |
Aug 23 09:58:25 PM UTC 24 |
1141193209 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.1741912142 |
|
|
Aug 23 09:58:20 PM UTC 24 |
Aug 23 09:58:25 PM UTC 24 |
275036489 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3088712609 |
|
|
Aug 23 09:58:23 PM UTC 24 |
Aug 23 09:58:27 PM UTC 24 |
1180995976 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3148725563 |
|
|
Aug 23 09:58:25 PM UTC 24 |
Aug 23 09:58:28 PM UTC 24 |
278657857 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1041018694 |
|
|
Aug 23 09:58:26 PM UTC 24 |
Aug 23 09:58:28 PM UTC 24 |
46423915 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_override.3271583067 |
|
|
Aug 23 09:58:27 PM UTC 24 |
Aug 23 09:58:29 PM UTC 24 |
24912610 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.4100824289 |
|
|
Aug 23 09:58:29 PM UTC 24 |
Aug 23 09:58:31 PM UTC 24 |
457336501 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.3027658689 |
|
|
Aug 23 09:58:17 PM UTC 24 |
Aug 23 09:58:34 PM UTC 24 |
2046664361 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2295937033 |
|
|
Aug 23 09:57:03 PM UTC 24 |
Aug 23 09:58:39 PM UTC 24 |
7440529052 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.80716732 |
|
|
Aug 23 09:55:32 PM UTC 24 |
Aug 23 09:58:39 PM UTC 24 |
24394829412 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.176510154 |
|
|
Aug 23 09:58:35 PM UTC 24 |
Aug 23 09:58:42 PM UTC 24 |
2184664011 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.1587655419 |
|
|
Aug 23 09:58:32 PM UTC 24 |
Aug 23 09:58:42 PM UTC 24 |
3991366903 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1730788511 |
|
|
Aug 23 09:58:26 PM UTC 24 |
Aug 23 09:58:52 PM UTC 24 |
1877429012 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.47528490 |
|
|
Aug 23 09:58:42 PM UTC 24 |
Aug 23 09:58:55 PM UTC 24 |
1365359773 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.590699541 |
|
|
Aug 23 09:58:53 PM UTC 24 |
Aug 23 09:58:57 PM UTC 24 |
211292356 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.3272485051 |
|
|
Aug 23 09:57:59 PM UTC 24 |
Aug 23 09:58:57 PM UTC 24 |
14031197753 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.4170662075 |
|
|
Aug 23 09:58:58 PM UTC 24 |
Aug 23 09:59:09 PM UTC 24 |
21789867330 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1455503535 |
|
|
Aug 23 09:57:43 PM UTC 24 |
Aug 23 09:59:11 PM UTC 24 |
47724156813 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2356435028 |
|
|
Aug 23 09:58:58 PM UTC 24 |
Aug 23 09:59:16 PM UTC 24 |
1744099662 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1759339485 |
|
|
Aug 23 09:59:10 PM UTC 24 |
Aug 23 09:59:17 PM UTC 24 |
728384465 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.310759293 |
|
|
Aug 23 09:59:17 PM UTC 24 |
Aug 23 09:59:23 PM UTC 24 |
7485617008 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.540608516 |
|
|
Aug 23 09:59:17 PM UTC 24 |
Aug 23 09:59:24 PM UTC 24 |
3891120100 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3024823980 |
|
|
Aug 23 09:58:42 PM UTC 24 |
Aug 23 09:59:26 PM UTC 24 |
1134475794 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1317233490 |
|
|
Aug 23 09:59:27 PM UTC 24 |
Aug 23 09:59:29 PM UTC 24 |
240756808 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.4154680633 |
|
|
Aug 23 09:59:28 PM UTC 24 |
Aug 23 09:59:30 PM UTC 24 |
324033070 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1751819293 |
|
|
Aug 23 09:59:24 PM UTC 24 |
Aug 23 09:59:32 PM UTC 24 |
2717719543 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.491479945 |
|
|
Aug 23 09:58:39 PM UTC 24 |
Aug 23 09:59:33 PM UTC 24 |
9200714656 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2455673623 |
|
|
Aug 23 09:59:30 PM UTC 24 |
Aug 23 09:59:36 PM UTC 24 |
802433124 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.1009616245 |
|
|
Aug 23 09:59:34 PM UTC 24 |
Aug 23 09:59:37 PM UTC 24 |
294038533 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3658537969 |
|
|
Aug 23 09:59:32 PM UTC 24 |
Aug 23 09:59:38 PM UTC 24 |
1082511504 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1872163917 |
|
|
Aug 23 09:59:12 PM UTC 24 |
Aug 23 09:59:42 PM UTC 24 |
1969990837 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.594040492 |
|
|
Aug 23 09:59:39 PM UTC 24 |
Aug 23 09:59:42 PM UTC 24 |
2374931209 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.1959973710 |
|
|
Aug 23 09:59:38 PM UTC 24 |
Aug 23 09:59:43 PM UTC 24 |
289762803 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3182992983 |
|
|
Aug 23 09:59:39 PM UTC 24 |
Aug 23 09:59:43 PM UTC 24 |
945872029 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2676931681 |
|
|
Aug 23 09:59:42 PM UTC 24 |
Aug 23 09:59:46 PM UTC 24 |
1105118856 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.1091000672 |
|
|
Aug 23 09:43:58 PM UTC 24 |
Aug 23 09:59:47 PM UTC 24 |
54564212068 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.3250363636 |
|
|
Aug 23 09:59:44 PM UTC 24 |
Aug 23 09:59:47 PM UTC 24 |
476877145 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1902330562 |
|
|
Aug 23 09:59:44 PM UTC 24 |
Aug 23 09:59:48 PM UTC 24 |
1159019477 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.1917391231 |
|
|
Aug 23 09:59:47 PM UTC 24 |
Aug 23 09:59:49 PM UTC 24 |
2351546442 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2999219288 |
|
|
Aug 23 09:59:48 PM UTC 24 |
Aug 23 09:59:49 PM UTC 24 |
40162809 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_override.2225619084 |
|
|
Aug 23 09:59:49 PM UTC 24 |
Aug 23 09:59:50 PM UTC 24 |
30462193 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3386904812 |
|
|
Aug 23 09:59:51 PM UTC 24 |
Aug 23 09:59:53 PM UTC 24 |
760215082 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2784800610 |
|
|
Aug 23 09:59:54 PM UTC 24 |
Aug 23 09:59:59 PM UTC 24 |
1236570334 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.117652810 |
|
|
Aug 23 09:59:42 PM UTC 24 |
Aug 23 10:00:10 PM UTC 24 |
2648162612 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.2525958306 |
|
|
Aug 23 10:00:11 PM UTC 24 |
Aug 23 10:00:14 PM UTC 24 |
284491195 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.1684232432 |
|
|
Aug 23 09:56:13 PM UTC 24 |
Aug 23 10:00:31 PM UTC 24 |
19760838587 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2400756733 |
|
|
Aug 23 10:00:32 PM UTC 24 |
Aug 23 10:00:35 PM UTC 24 |
378761369 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3708747969 |
|
|
Aug 23 09:58:28 PM UTC 24 |
Aug 23 10:00:35 PM UTC 24 |
2407217831 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.584891058 |
|
|
Aug 23 10:00:14 PM UTC 24 |
Aug 23 10:00:38 PM UTC 24 |
2306865723 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.2190386959 |
|
|
Aug 23 09:59:48 PM UTC 24 |
Aug 23 10:00:51 PM UTC 24 |
1611519585 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.850273412 |
|
|
Aug 23 10:00:35 PM UTC 24 |
Aug 23 10:00:52 PM UTC 24 |
1572648565 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.3620405927 |
|
|
Aug 23 10:00:53 PM UTC 24 |
Aug 23 10:00:57 PM UTC 24 |
1768786833 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.1977153401 |
|
|
Aug 23 10:00:58 PM UTC 24 |
Aug 23 10:01:04 PM UTC 24 |
1718056744 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1830315929 |
|
|
Aug 23 10:00:10 PM UTC 24 |
Aug 23 10:01:05 PM UTC 24 |
9297657204 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.252079962 |
|
|
Aug 23 10:01:05 PM UTC 24 |
Aug 23 10:01:10 PM UTC 24 |
6457151727 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.4119726867 |
|
|
Aug 23 09:59:50 PM UTC 24 |
Aug 23 10:01:13 PM UTC 24 |
6645370219 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.471639189 |
|
|
Aug 23 10:01:06 PM UTC 24 |
Aug 23 10:01:14 PM UTC 24 |
2816430017 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.2739358713 |
|
|
Aug 23 09:59:50 PM UTC 24 |
Aug 23 10:01:14 PM UTC 24 |
3802072863 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3455458196 |
|
|
Aug 23 10:01:14 PM UTC 24 |
Aug 23 10:01:16 PM UTC 24 |
216029113 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.238291304 |
|
|
Aug 23 10:01:14 PM UTC 24 |
Aug 23 10:01:16 PM UTC 24 |
240849514 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_perf.617503036 |
|
|
Aug 23 10:01:15 PM UTC 24 |
Aug 23 10:01:22 PM UTC 24 |
3617965787 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1718143764 |
|
|
Aug 23 10:01:17 PM UTC 24 |
Aug 23 10:01:25 PM UTC 24 |
1416943541 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_mode_toggle.377484600 |
|
|
Aug 23 10:01:23 PM UTC 24 |
Aug 23 10:01:27 PM UTC 24 |
131776932 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.22929265 |
|
|
Aug 23 10:01:27 PM UTC 24 |
Aug 23 10:01:30 PM UTC 24 |
678309395 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.240019051 |
|
|
Aug 23 10:01:25 PM UTC 24 |
Aug 23 10:01:32 PM UTC 24 |
512371005 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.3956947447 |
|
|
Aug 23 09:53:09 PM UTC 24 |
Aug 23 10:01:33 PM UTC 24 |
50065501072 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3857454662 |
|
|
Aug 23 09:58:28 PM UTC 24 |
Aug 23 10:01:33 PM UTC 24 |
3893256867 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3265257335 |
|
|
Aug 23 10:01:32 PM UTC 24 |
Aug 23 10:01:37 PM UTC 24 |
159857437 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.1922391518 |
|
|
Aug 23 10:01:33 PM UTC 24 |
Aug 23 10:01:37 PM UTC 24 |
450118776 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3978964385 |
|
|
Aug 23 10:01:33 PM UTC 24 |
Aug 23 10:01:37 PM UTC 24 |
2438219663 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.428784641 |
|
|
Aug 23 10:01:33 PM UTC 24 |
Aug 23 10:01:37 PM UTC 24 |
1988205328 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1586015192 |
|
|
Aug 23 10:01:38 PM UTC 24 |
Aug 23 10:01:39 PM UTC 24 |
37655927 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.105209472 |
|
|
Aug 23 10:03:06 PM UTC 24 |
Aug 23 10:03:20 PM UTC 24 |
991237531 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_override.552677077 |
|
|
Aug 23 10:01:39 PM UTC 24 |
Aug 23 10:01:40 PM UTC 24 |
30558386 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.441399067 |
|
|
Aug 23 10:01:41 PM UTC 24 |
Aug 23 10:01:43 PM UTC 24 |
81861244 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3066589179 |
|
|
Aug 23 10:00:52 PM UTC 24 |
Aug 23 10:01:48 PM UTC 24 |
1385001193 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.905289632 |
|
|
Aug 23 10:01:49 PM UTC 24 |
Aug 23 10:01:53 PM UTC 24 |
294396805 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.804952618 |
|
|
Aug 23 09:58:12 PM UTC 24 |
Aug 23 10:02:03 PM UTC 24 |
35833268135 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.244519406 |
|
|
Aug 23 10:01:38 PM UTC 24 |
Aug 23 10:02:04 PM UTC 24 |
3106058741 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1079427023 |
|
|
Aug 23 10:00:10 PM UTC 24 |
Aug 23 10:02:06 PM UTC 24 |
50568298633 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.833168811 |
|
|
Aug 23 10:02:02 PM UTC 24 |
Aug 23 10:02:07 PM UTC 24 |
221749181 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.854279811 |
|
|
Aug 23 10:02:05 PM UTC 24 |
Aug 23 10:02:08 PM UTC 24 |
76520897 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1655425612 |
|
|
Aug 23 10:01:43 PM UTC 24 |
Aug 23 10:02:08 PM UTC 24 |
1098559570 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2795099375 |
|
|
Aug 23 10:01:41 PM UTC 24 |
Aug 23 10:02:17 PM UTC 24 |
1598906552 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.97175914 |
|
|
Aug 23 10:02:08 PM UTC 24 |
Aug 23 10:02:20 PM UTC 24 |
783250826 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_perf.2852635406 |
|
|
Aug 23 10:01:54 PM UTC 24 |
Aug 23 10:02:21 PM UTC 24 |
2758377387 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.789515968 |
|
|
Aug 23 10:02:08 PM UTC 24 |
Aug 23 10:02:25 PM UTC 24 |
886098733 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.16020839 |
|
|
Aug 23 10:02:17 PM UTC 24 |
Aug 23 10:02:25 PM UTC 24 |
998809632 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2918884136 |
|
|
Aug 23 10:01:15 PM UTC 24 |
Aug 23 10:02:25 PM UTC 24 |
17726053444 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.3326456515 |
|
|
Aug 23 10:02:20 PM UTC 24 |
Aug 23 10:02:26 PM UTC 24 |
829009171 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.2738521144 |
|
|
Aug 23 10:02:26 PM UTC 24 |
Aug 23 10:02:28 PM UTC 24 |
973982097 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1280581094 |
|
|
Aug 23 10:02:27 PM UTC 24 |
Aug 23 10:02:29 PM UTC 24 |
165706289 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.942149901 |
|
|
Aug 23 10:02:22 PM UTC 24 |
Aug 23 10:02:33 PM UTC 24 |
16922133043 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3349289417 |
|
|
Aug 23 10:02:29 PM UTC 24 |
Aug 23 10:02:33 PM UTC 24 |
4128784727 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1981473894 |
|
|
Aug 23 10:02:26 PM UTC 24 |
Aug 23 10:02:34 PM UTC 24 |
7805446506 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.1563420975 |
|
|
Aug 23 10:01:40 PM UTC 24 |
Aug 23 10:02:34 PM UTC 24 |
3075430223 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2972661801 |
|
|
Aug 23 10:02:04 PM UTC 24 |
Aug 23 10:02:35 PM UTC 24 |
1452192115 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3961321788 |
|
|
Aug 23 10:02:30 PM UTC 24 |
Aug 23 10:02:36 PM UTC 24 |
3679239468 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3471555073 |
|
|
Aug 23 10:02:34 PM UTC 24 |
Aug 23 10:02:37 PM UTC 24 |
261292646 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1253382917 |
|
|
Aug 23 10:02:34 PM UTC 24 |
Aug 23 10:02:38 PM UTC 24 |
1090168856 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.4066837564 |
|
|
Aug 23 10:02:36 PM UTC 24 |
Aug 23 10:02:38 PM UTC 24 |
658093953 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2085698813 |
|
|
Aug 23 10:02:35 PM UTC 24 |
Aug 23 10:02:39 PM UTC 24 |
2957127286 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3547370861 |
|
|
Aug 23 10:02:37 PM UTC 24 |
Aug 23 10:02:40 PM UTC 24 |
852717685 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.1518494691 |
|
|
Aug 23 10:02:37 PM UTC 24 |
Aug 23 10:02:40 PM UTC 24 |
122730180 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.720809598 |
|
|
Aug 23 10:03:09 PM UTC 24 |
Aug 23 10:03:25 PM UTC 24 |
5244905661 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.697720321 |
|
|
Aug 23 10:02:38 PM UTC 24 |
Aug 23 10:02:42 PM UTC 24 |
554854455 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_alert_test.2668704596 |
|
|
Aug 23 10:02:40 PM UTC 24 |
Aug 23 10:02:42 PM UTC 24 |
19032441 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.786688223 |
|
|
Aug 23 10:02:39 PM UTC 24 |
Aug 23 10:02:42 PM UTC 24 |
1905557041 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_override.1773135587 |
|
|
Aug 23 10:02:42 PM UTC 24 |
Aug 23 10:02:44 PM UTC 24 |
82023004 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.3254381237 |
|
|
Aug 23 10:02:43 PM UTC 24 |
Aug 23 10:02:45 PM UTC 24 |
752534019 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.1930431061 |
|
|
Aug 23 09:54:35 PM UTC 24 |
Aug 23 10:02:48 PM UTC 24 |
65742753942 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2321165862 |
|
|
Aug 23 10:02:46 PM UTC 24 |
Aug 23 10:02:52 PM UTC 24 |
1459501392 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1587204878 |
|
|
Aug 23 10:02:45 PM UTC 24 |
Aug 23 10:02:52 PM UTC 24 |
5798719103 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.4062711315 |
|
|
Aug 23 10:02:53 PM UTC 24 |
Aug 23 10:02:57 PM UTC 24 |
229646699 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2720918168 |
|
|
Aug 23 10:02:35 PM UTC 24 |
Aug 23 10:02:58 PM UTC 24 |
2615913041 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2615005840 |
|
|
Aug 23 10:02:59 PM UTC 24 |
Aug 23 10:03:02 PM UTC 24 |
121737854 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1020851710 |
|
|
Aug 23 10:02:58 PM UTC 24 |
Aug 23 10:03:05 PM UTC 24 |
432878540 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.88913789 |
|
|
Aug 23 09:51:57 PM UTC 24 |
Aug 23 10:03:07 PM UTC 24 |
31358563996 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2178865050 |
|
|
Aug 23 10:01:51 PM UTC 24 |
Aug 23 10:03:09 PM UTC 24 |
3467657061 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/46.i2c_host_perf.3951929775 |
|
|
Aug 23 09:58:40 PM UTC 24 |
Aug 23 10:03:10 PM UTC 24 |
6121011259 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.981028696 |
|
|
Aug 23 10:03:11 PM UTC 24 |
Aug 23 10:03:19 PM UTC 24 |
2636780818 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.940743581 |
|
|
Aug 23 10:02:29 PM UTC 24 |
Aug 23 10:03:20 PM UTC 24 |
74202473319 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.712517628 |
|
|
Aug 23 10:03:24 PM UTC 24 |
Aug 23 10:03:26 PM UTC 24 |
321305983 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1317994912 |
|
|
Aug 23 10:03:20 PM UTC 24 |
Aug 23 10:03:27 PM UTC 24 |
6690839216 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.2071824991 |
|
|
Aug 23 10:03:25 PM UTC 24 |
Aug 23 10:03:28 PM UTC 24 |
320321370 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.217490876 |
|
|
Aug 23 10:03:21 PM UTC 24 |
Aug 23 10:03:28 PM UTC 24 |
4750953405 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.3517879080 |
|
|
Aug 23 10:03:30 PM UTC 24 |
Aug 23 10:03:32 PM UTC 24 |
719720244 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2733017260 |
|
|
Aug 23 10:03:30 PM UTC 24 |
Aug 23 10:03:34 PM UTC 24 |
5861369745 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_perf.3889328815 |
|
|
Aug 23 10:03:27 PM UTC 24 |
Aug 23 10:03:35 PM UTC 24 |
3757411606 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1695639936 |
|
|
Aug 23 10:02:08 PM UTC 24 |
Aug 23 10:03:37 PM UTC 24 |
54178035749 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1668499759 |
|
|
Aug 23 10:03:08 PM UTC 24 |
Aug 23 10:03:37 PM UTC 24 |
15584776397 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2137847157 |
|
|
Aug 23 10:03:33 PM UTC 24 |
Aug 23 10:03:38 PM UTC 24 |
138188144 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1136474573 |
|
|
Aug 23 10:02:41 PM UTC 24 |
Aug 23 10:03:39 PM UTC 24 |
5384361137 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1620339278 |
|
|
Aug 23 10:03:36 PM UTC 24 |
Aug 23 10:03:40 PM UTC 24 |
1415499408 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.559369912 |
|
|
Aug 23 10:03:38 PM UTC 24 |
Aug 23 10:03:40 PM UTC 24 |
462890994 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1331162407 |
|
|
Aug 23 10:03:39 PM UTC 24 |
Aug 23 10:03:42 PM UTC 24 |
3582358617 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.2348909076 |
|
|
Aug 23 10:03:41 PM UTC 24 |
Aug 23 10:03:43 PM UTC 24 |
139850531 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2219753972 |
|
|
Aug 23 10:03:40 PM UTC 24 |
Aug 23 10:03:43 PM UTC 24 |
480089977 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.2716670660 |
|
|
Aug 23 10:03:40 PM UTC 24 |
Aug 23 10:03:44 PM UTC 24 |
5159597293 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.11945924 |
|
|
Aug 23 10:03:20 PM UTC 24 |
Aug 23 10:03:45 PM UTC 24 |
3513703334 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.3723925621 |
|
|
Aug 23 10:03:38 PM UTC 24 |
Aug 23 10:03:45 PM UTC 24 |
452672030 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2999357391 |
|
|
Aug 23 10:03:43 PM UTC 24 |
Aug 23 10:03:45 PM UTC 24 |
19962973 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2600479983 |
|
|
Aug 23 10:02:42 PM UTC 24 |
Aug 23 10:03:45 PM UTC 24 |
15991676992 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.4264685640 |
|
|
Aug 23 10:02:42 PM UTC 24 |
Aug 23 10:03:55 PM UTC 24 |
2937885343 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3491986529 |
|
|
Aug 23 10:03:35 PM UTC 24 |
Aug 23 10:04:02 PM UTC 24 |
770257317 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/37.i2c_host_perf.782211004 |
|
|
Aug 23 09:48:47 PM UTC 24 |
Aug 23 10:04:35 PM UTC 24 |
26808929781 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3768459812 |
|
|
Aug 23 10:03:28 PM UTC 24 |
Aug 23 10:05:11 PM UTC 24 |
46705264693 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.3248576859 |
|
|
Aug 23 10:02:49 PM UTC 24 |
Aug 23 10:05:20 PM UTC 24 |
12293620469 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.2643474648 |
|
|
Aug 23 09:42:48 PM UTC 24 |
Aug 23 10:06:59 PM UTC 24 |
66848242622 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/43.i2c_host_stress_all.1266920447 |
|
|
Aug 23 09:54:29 PM UTC 24 |
Aug 23 10:08:14 PM UTC 24 |
11500551776 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1420448611 |
|
|
Aug 23 10:00:38 PM UTC 24 |
Aug 23 10:08:18 PM UTC 24 |
44651652855 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/49.i2c_host_perf.2345286239 |
|
|
Aug 23 10:02:53 PM UTC 24 |
Aug 23 10:08:51 PM UTC 24 |
12921923030 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3230217694 |
|
|
Aug 23 09:56:29 PM UTC 24 |
Aug 23 10:09:05 PM UTC 24 |
47050090443 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.4168952188 |
|
|
Aug 23 09:57:17 PM UTC 24 |
Aug 23 10:09:25 PM UTC 24 |
80995263873 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.196103287 |
|
|
Aug 23 09:45:13 PM UTC 24 |
Aug 23 10:19:37 PM UTC 24 |
24730857242 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/44.i2c_host_perf.3933314460 |
|
|
Aug 23 09:55:40 PM UTC 24 |
Aug 23 10:39:12 PM UTC 24 |
72727524479 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/default/42.i2c_host_perf.3294910393 |
|
|
Aug 23 09:53:26 PM UTC 24 |
Aug 23 10:47:07 PM UTC 24 |
48081573744 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.4062412618 |
|
|
Aug 23 10:03:44 PM UTC 24 |
Aug 23 10:03:47 PM UTC 24 |
67546638 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2288523198 |
|
|
Aug 23 10:03:44 PM UTC 24 |
Aug 23 10:03:47 PM UTC 24 |
241312652 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1706829083 |
|
|
Aug 23 10:03:45 PM UTC 24 |
Aug 23 10:03:47 PM UTC 24 |
83803872 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3945907337 |
|
|
Aug 23 10:03:45 PM UTC 24 |
Aug 23 10:03:47 PM UTC 24 |
16834198 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.2799655741 |
|
|
Aug 23 10:03:45 PM UTC 24 |
Aug 23 10:03:47 PM UTC 24 |
22146082 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.430113575 |
|
|
Aug 23 10:03:45 PM UTC 24 |
Aug 23 10:03:48 PM UTC 24 |
136875486 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.518355826 |
|
|
Aug 23 10:03:46 PM UTC 24 |
Aug 23 10:03:49 PM UTC 24 |
138896644 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4040265441 |
|
|
Aug 23 10:03:47 PM UTC 24 |
Aug 23 10:03:50 PM UTC 24 |
33186053 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3926766190 |
|
|
Aug 23 10:03:47 PM UTC 24 |
Aug 23 10:03:50 PM UTC 24 |
31559674 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.925915901 |
|
|
Aug 23 10:03:47 PM UTC 24 |
Aug 23 10:03:50 PM UTC 24 |
125192951 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1069762014 |
|
|
Aug 23 10:03:48 PM UTC 24 |
Aug 23 10:03:50 PM UTC 24 |
41804374 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3743522886 |
|
|
Aug 23 10:03:49 PM UTC 24 |
Aug 23 10:03:51 PM UTC 24 |
47191248 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1206894882 |
|
|
Aug 23 10:03:45 PM UTC 24 |
Aug 23 10:03:51 PM UTC 24 |
113392352 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.1028717944 |
|
|
Aug 23 10:03:50 PM UTC 24 |
Aug 23 10:03:51 PM UTC 24 |
21716351 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3994029526 |
|
|
Aug 23 10:03:51 PM UTC 24 |
Aug 23 10:03:53 PM UTC 24 |
40617782 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1941671299 |
|
|
Aug 23 10:03:51 PM UTC 24 |
Aug 23 10:03:53 PM UTC 24 |
51419709 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3934078242 |
|
|
Aug 23 10:03:51 PM UTC 24 |
Aug 23 10:03:53 PM UTC 24 |
228691526 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.2611466232 |
|
|
Aug 23 10:03:52 PM UTC 24 |
Aug 23 10:03:54 PM UTC 24 |
50088671 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.3135682433 |
|
|
Aug 23 10:03:52 PM UTC 24 |
Aug 23 10:03:54 PM UTC 24 |
114910201 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2984217806 |
|
|
Aug 23 10:03:51 PM UTC 24 |
Aug 23 10:03:54 PM UTC 24 |
1426014970 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.514340531 |
|
|
Aug 23 10:03:53 PM UTC 24 |
Aug 23 10:03:55 PM UTC 24 |
53409246 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.866483806 |
|
|
Aug 23 10:03:52 PM UTC 24 |
Aug 23 10:03:55 PM UTC 24 |
583699065 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.2819698685 |
|
|
Aug 23 10:03:50 PM UTC 24 |
Aug 23 10:03:55 PM UTC 24 |
1396496225 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1859936149 |
|
|
Aug 23 10:03:54 PM UTC 24 |
Aug 23 10:03:56 PM UTC 24 |
106308146 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.412589239 |
|
|
Aug 23 10:03:54 PM UTC 24 |
Aug 23 10:03:56 PM UTC 24 |
104180401 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.1857572021 |
|
|
Aug 23 10:03:55 PM UTC 24 |
Aug 23 10:03:57 PM UTC 24 |
19813595 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1070859368 |
|
|
Aug 23 10:03:54 PM UTC 24 |
Aug 23 10:03:57 PM UTC 24 |
359681841 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3584735249 |
|
|
Aug 23 10:03:53 PM UTC 24 |
Aug 23 10:03:58 PM UTC 24 |
233354741 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.546197758 |
|
|
Aug 23 10:03:56 PM UTC 24 |
Aug 23 10:03:58 PM UTC 24 |
40356386 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.502902757 |
|
|
Aug 23 10:03:56 PM UTC 24 |
Aug 23 10:03:58 PM UTC 24 |
20161658 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.266299313 |
|
|
Aug 23 10:03:55 PM UTC 24 |
Aug 23 10:03:58 PM UTC 24 |
1299938736 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.1953874720 |
|
|
Aug 23 10:03:55 PM UTC 24 |
Aug 23 10:03:58 PM UTC 24 |
565082104 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3102145192 |
|
|
Aug 23 10:03:57 PM UTC 24 |
Aug 23 10:03:59 PM UTC 24 |
287087406 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.2350475725 |
|
|
Aug 23 10:03:57 PM UTC 24 |
Aug 23 10:04:00 PM UTC 24 |
148422906 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3062119053 |
|
|
Aug 23 10:03:58 PM UTC 24 |
Aug 23 10:04:00 PM UTC 24 |
31279621 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3838961232 |
|
|
Aug 23 10:03:59 PM UTC 24 |
Aug 23 10:04:00 PM UTC 24 |
17647080 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.588206238 |
|
|
Aug 23 10:03:59 PM UTC 24 |
Aug 23 10:04:01 PM UTC 24 |
37873067 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.587280059 |
|
|
Aug 23 10:03:59 PM UTC 24 |
Aug 23 10:04:01 PM UTC 24 |
67654235 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.1396721021 |
|
|
Aug 23 10:03:59 PM UTC 24 |
Aug 23 10:04:01 PM UTC 24 |
55680929 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.1051310512 |
|
|
Aug 23 10:04:11 PM UTC 24 |
Aug 23 10:04:13 PM UTC 24 |
44038184 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2757088596 |
|
|
Aug 23 10:03:59 PM UTC 24 |
Aug 23 10:04:01 PM UTC 24 |
256604319 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.4209805489 |
|
|
Aug 23 10:03:56 PM UTC 24 |
Aug 23 10:04:02 PM UTC 24 |
754509486 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2917498652 |
|
|
Aug 23 10:04:01 PM UTC 24 |
Aug 23 10:04:03 PM UTC 24 |
37248016 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1976062154 |
|
|
Aug 23 10:04:01 PM UTC 24 |
Aug 23 10:04:03 PM UTC 24 |
59359813 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1241444756 |
|
|
Aug 23 10:04:01 PM UTC 24 |
Aug 23 10:04:03 PM UTC 24 |
241011222 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.4009330691 |
|
|
Aug 23 10:04:02 PM UTC 24 |
Aug 23 10:04:04 PM UTC 24 |
40902831 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2238548602 |
|
|
Aug 23 10:04:01 PM UTC 24 |
Aug 23 10:04:04 PM UTC 24 |
38207887 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3007168456 |
|
|
Aug 23 10:04:02 PM UTC 24 |
Aug 23 10:04:04 PM UTC 24 |
28974415 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.1984539273 |
|
|
Aug 23 10:04:01 PM UTC 24 |
Aug 23 10:04:04 PM UTC 24 |
490388382 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.573185823 |
|
|
Aug 23 10:04:00 PM UTC 24 |
Aug 23 10:04:05 PM UTC 24 |
229392673 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3722375202 |
|
|
Aug 23 10:04:03 PM UTC 24 |
Aug 23 10:04:05 PM UTC 24 |
31966930 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.772187380 |
|
|
Aug 23 10:04:03 PM UTC 24 |
Aug 23 10:04:05 PM UTC 24 |
28010685 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1372195139 |
|
|
Aug 23 10:04:05 PM UTC 24 |
Aug 23 10:04:06 PM UTC 24 |
18725603 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3793333826 |
|
|
Aug 23 10:04:05 PM UTC 24 |
Aug 23 10:04:07 PM UTC 24 |
28129380 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.307111306 |
|
|
Aug 23 10:04:05 PM UTC 24 |
Aug 23 10:04:07 PM UTC 24 |
95030310 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1499251602 |
|
|
Aug 23 10:04:03 PM UTC 24 |
Aug 23 10:04:07 PM UTC 24 |
1007275312 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3110450906 |
|
|
Aug 23 10:04:05 PM UTC 24 |
Aug 23 10:04:07 PM UTC 24 |
112561432 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1711005224 |
|
|
Aug 23 10:04:03 PM UTC 24 |
Aug 23 10:04:07 PM UTC 24 |
256921624 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2820428494 |
|
|
Aug 23 10:04:06 PM UTC 24 |
Aug 23 10:04:08 PM UTC 24 |
15566782 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1734015737 |
|
|
Aug 23 10:04:06 PM UTC 24 |
Aug 23 10:04:08 PM UTC 24 |
42182901 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3777034758 |
|
|
Aug 23 10:04:05 PM UTC 24 |
Aug 23 10:04:08 PM UTC 24 |
423592295 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.759411652 |
|
|
Aug 23 10:04:06 PM UTC 24 |
Aug 23 10:04:08 PM UTC 24 |
328450064 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.2956982155 |
|
|
Aug 23 10:04:07 PM UTC 24 |
Aug 23 10:04:09 PM UTC 24 |
24254145 ps |