| T89 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.1604302101 |
|
|
Sep 11 05:35:08 AM UTC 24 |
Sep 11 05:35:11 AM UTC 24 |
316206246 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_perf.1815895561 |
|
|
Sep 11 05:35:08 AM UTC 24 |
Sep 11 05:35:13 AM UTC 24 |
526970338 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.4268030189 |
|
|
Sep 11 05:34:19 AM UTC 24 |
Sep 11 05:35:31 AM UTC 24 |
4925857021 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.61897239 |
|
|
Sep 11 05:35:04 AM UTC 24 |
Sep 11 05:35:14 AM UTC 24 |
2328215846 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.3570455481 |
|
|
Sep 11 05:33:15 AM UTC 24 |
Sep 11 05:35:16 AM UTC 24 |
5230269010 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/12.i2c_host_perf.2647528102 |
|
|
Sep 11 05:13:56 AM UTC 24 |
Sep 11 05:40:27 AM UTC 24 |
26333522969 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/36.i2c_host_stress_all.2931915452 |
|
|
Sep 11 05:29:40 AM UTC 24 |
Sep 11 05:35:18 AM UTC 24 |
38872594086 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.148360529 |
|
|
Sep 11 05:35:15 AM UTC 24 |
Sep 11 05:35:18 AM UTC 24 |
381481378 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.4019603923 |
|
|
Sep 11 05:35:09 AM UTC 24 |
Sep 11 05:35:20 AM UTC 24 |
4971554790 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.2986627387 |
|
|
Sep 11 05:34:51 AM UTC 24 |
Sep 11 05:35:20 AM UTC 24 |
479964180 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.1642882347 |
|
|
Sep 11 05:35:12 AM UTC 24 |
Sep 11 05:35:20 AM UTC 24 |
881011819 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.1823854728 |
|
|
Sep 11 05:35:13 AM UTC 24 |
Sep 11 05:35:21 AM UTC 24 |
602786202 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.392446974 |
|
|
Sep 11 05:35:17 AM UTC 24 |
Sep 11 05:35:22 AM UTC 24 |
2192328856 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.1814171806 |
|
|
Sep 11 05:35:19 AM UTC 24 |
Sep 11 05:35:22 AM UTC 24 |
1080828645 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.501404507 |
|
|
Sep 11 05:35:15 AM UTC 24 |
Sep 11 05:35:23 AM UTC 24 |
185651102 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_alert_test.303521137 |
|
|
Sep 11 05:35:21 AM UTC 24 |
Sep 11 05:35:23 AM UTC 24 |
151080662 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_override.1746068276 |
|
|
Sep 11 05:35:21 AM UTC 24 |
Sep 11 05:35:23 AM UTC 24 |
17150870 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.3264851045 |
|
|
Sep 11 05:32:41 AM UTC 24 |
Sep 11 05:35:24 AM UTC 24 |
40478572743 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.4242400562 |
|
|
Sep 11 05:35:18 AM UTC 24 |
Sep 11 05:35:24 AM UTC 24 |
1138107904 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.575065772 |
|
|
Sep 11 05:35:19 AM UTC 24 |
Sep 11 05:35:26 AM UTC 24 |
632138437 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.1747241353 |
|
|
Sep 11 05:35:24 AM UTC 24 |
Sep 11 05:35:26 AM UTC 24 |
1184412343 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/22.i2c_host_perf.3564341836 |
|
|
Sep 11 05:20:34 AM UTC 24 |
Sep 11 05:40:36 AM UTC 24 |
29527800191 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.544493091 |
|
|
Sep 11 05:35:45 AM UTC 24 |
Sep 11 05:35:49 AM UTC 24 |
1534005126 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.460365624 |
|
|
Sep 11 05:35:47 AM UTC 24 |
Sep 11 05:35:50 AM UTC 24 |
157049509 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.3678085032 |
|
|
Sep 11 05:37:19 AM UTC 24 |
Sep 11 05:37:27 AM UTC 24 |
4144733840 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.1506481217 |
|
|
Sep 11 05:35:42 AM UTC 24 |
Sep 11 05:35:53 AM UTC 24 |
2016851456 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.450230580 |
|
|
Sep 11 05:35:48 AM UTC 24 |
Sep 11 05:35:53 AM UTC 24 |
650385738 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.651714363 |
|
|
Sep 11 05:35:03 AM UTC 24 |
Sep 11 05:35:55 AM UTC 24 |
10584458150 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1588839217 |
|
|
Sep 11 05:35:55 AM UTC 24 |
Sep 11 05:35:57 AM UTC 24 |
180707452 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2318511588 |
|
|
Sep 11 05:35:55 AM UTC 24 |
Sep 11 05:35:58 AM UTC 24 |
57024074 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_perf.1619016613 |
|
|
Sep 11 05:35:47 AM UTC 24 |
Sep 11 05:35:58 AM UTC 24 |
4868988000 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.613169651 |
|
|
Sep 11 05:35:50 AM UTC 24 |
Sep 11 05:35:58 AM UTC 24 |
639998292 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.584006574 |
|
|
Sep 11 05:35:34 AM UTC 24 |
Sep 11 05:35:59 AM UTC 24 |
1013245407 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.364104778 |
|
|
Sep 11 05:35:53 AM UTC 24 |
Sep 11 05:35:59 AM UTC 24 |
532821954 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1079469818 |
|
|
Sep 11 05:35:27 AM UTC 24 |
Sep 11 05:36:00 AM UTC 24 |
2221873092 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2628019905 |
|
|
Sep 11 05:35:56 AM UTC 24 |
Sep 11 05:36:00 AM UTC 24 |
1649379894 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_perf.234002338 |
|
|
Sep 11 05:37:18 AM UTC 24 |
Sep 11 05:37:28 AM UTC 24 |
847190052 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_alert_test.2291643871 |
|
|
Sep 11 05:35:59 AM UTC 24 |
Sep 11 05:36:01 AM UTC 24 |
15770337 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.1543487992 |
|
|
Sep 11 05:35:59 AM UTC 24 |
Sep 11 05:36:02 AM UTC 24 |
142787903 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.1437404469 |
|
|
Sep 11 05:35:58 AM UTC 24 |
Sep 11 05:36:02 AM UTC 24 |
1115614514 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_override.310531479 |
|
|
Sep 11 05:36:00 AM UTC 24 |
Sep 11 05:36:02 AM UTC 24 |
98531282 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.3666348757 |
|
|
Sep 11 05:34:49 AM UTC 24 |
Sep 11 05:36:03 AM UTC 24 |
11610517386 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1210869142 |
|
|
Sep 11 05:35:59 AM UTC 24 |
Sep 11 05:36:04 AM UTC 24 |
441053654 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1853956942 |
|
|
Sep 11 05:37:04 AM UTC 24 |
Sep 11 05:37:28 AM UTC 24 |
9787437971 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.1166661606 |
|
|
Sep 11 05:36:02 AM UTC 24 |
Sep 11 05:36:05 AM UTC 24 |
329497295 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3870907845 |
|
|
Sep 11 05:36:04 AM UTC 24 |
Sep 11 05:36:07 AM UTC 24 |
41711863 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.488253279 |
|
|
Sep 11 05:36:04 AM UTC 24 |
Sep 11 05:36:10 AM UTC 24 |
355817919 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.167186443 |
|
|
Sep 11 05:36:06 AM UTC 24 |
Sep 11 05:36:12 AM UTC 24 |
373076045 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.3347623456 |
|
|
Sep 11 05:33:14 AM UTC 24 |
Sep 11 05:36:12 AM UTC 24 |
21458979615 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2827244899 |
|
|
Sep 11 05:35:25 AM UTC 24 |
Sep 11 05:36:16 AM UTC 24 |
3054840686 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3337163876 |
|
|
Sep 11 05:36:02 AM UTC 24 |
Sep 11 05:36:17 AM UTC 24 |
1010388489 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.1123025391 |
|
|
Sep 11 05:34:46 AM UTC 24 |
Sep 11 05:36:22 AM UTC 24 |
12163668460 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.178902450 |
|
|
Sep 11 05:36:19 AM UTC 24 |
Sep 11 05:36:25 AM UTC 24 |
9529933730 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2044357310 |
|
|
Sep 11 05:36:10 AM UTC 24 |
Sep 11 05:36:25 AM UTC 24 |
710675636 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.2845873805 |
|
|
Sep 11 05:24:27 AM UTC 24 |
Sep 11 05:36:27 AM UTC 24 |
78454915475 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1022216016 |
|
|
Sep 11 05:37:27 AM UTC 24 |
Sep 11 05:37:29 AM UTC 24 |
74266706 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2534280136 |
|
|
Sep 11 05:36:17 AM UTC 24 |
Sep 11 05:36:28 AM UTC 24 |
6148821941 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.4180421827 |
|
|
Sep 11 05:36:27 AM UTC 24 |
Sep 11 05:36:29 AM UTC 24 |
227551542 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.3037416526 |
|
|
Sep 11 05:31:41 AM UTC 24 |
Sep 11 05:36:30 AM UTC 24 |
17991442126 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1183573562 |
|
|
Sep 11 05:36:28 AM UTC 24 |
Sep 11 05:36:30 AM UTC 24 |
225364210 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.3922887242 |
|
|
Sep 11 05:36:23 AM UTC 24 |
Sep 11 05:36:32 AM UTC 24 |
5775575950 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.3735502678 |
|
|
Sep 11 05:35:21 AM UTC 24 |
Sep 11 05:36:33 AM UTC 24 |
2724204122 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2603569805 |
|
|
Sep 11 05:36:29 AM UTC 24 |
Sep 11 05:36:38 AM UTC 24 |
3482127389 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3638531427 |
|
|
Sep 11 05:35:25 AM UTC 24 |
Sep 11 05:36:39 AM UTC 24 |
2461973100 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.654350997 |
|
|
Sep 11 05:36:37 AM UTC 24 |
Sep 11 05:36:40 AM UTC 24 |
213663259 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.4269340551 |
|
|
Sep 11 05:36:34 AM UTC 24 |
Sep 11 05:36:41 AM UTC 24 |
549156080 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3983248297 |
|
|
Sep 11 05:36:39 AM UTC 24 |
Sep 11 05:36:42 AM UTC 24 |
92768702 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1981084353 |
|
|
Sep 11 05:36:12 AM UTC 24 |
Sep 11 05:36:43 AM UTC 24 |
2374471752 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1372552253 |
|
|
Sep 11 05:36:30 AM UTC 24 |
Sep 11 05:36:44 AM UTC 24 |
5053857473 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1462671651 |
|
|
Sep 11 05:36:41 AM UTC 24 |
Sep 11 05:36:45 AM UTC 24 |
4931723395 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2850665148 |
|
|
Sep 11 05:36:40 AM UTC 24 |
Sep 11 05:36:45 AM UTC 24 |
1044941900 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.3511858978 |
|
|
Sep 11 05:36:00 AM UTC 24 |
Sep 11 05:36:45 AM UTC 24 |
1906728417 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_alert_test.379346893 |
|
|
Sep 11 05:36:44 AM UTC 24 |
Sep 11 05:36:46 AM UTC 24 |
23129441 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.3807497143 |
|
|
Sep 11 05:36:42 AM UTC 24 |
Sep 11 05:36:48 AM UTC 24 |
2980016635 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_override.35209604 |
|
|
Sep 11 05:36:46 AM UTC 24 |
Sep 11 05:36:48 AM UTC 24 |
74470908 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.2817662355 |
|
|
Sep 11 05:36:47 AM UTC 24 |
Sep 11 05:36:50 AM UTC 24 |
312479873 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2009387683 |
|
|
Sep 11 05:36:05 AM UTC 24 |
Sep 11 05:36:53 AM UTC 24 |
844456883 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.1376429794 |
|
|
Sep 11 05:36:47 AM UTC 24 |
Sep 11 05:36:53 AM UTC 24 |
435675305 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.955642247 |
|
|
Sep 11 05:35:22 AM UTC 24 |
Sep 11 05:36:54 AM UTC 24 |
4056905611 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.1809407526 |
|
|
Sep 11 05:36:33 AM UTC 24 |
Sep 11 05:36:55 AM UTC 24 |
413484351 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.1392904398 |
|
|
Sep 11 05:36:55 AM UTC 24 |
Sep 11 05:36:58 AM UTC 24 |
194444432 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.2902695397 |
|
|
Sep 11 05:27:48 AM UTC 24 |
Sep 11 05:37:03 AM UTC 24 |
63090437501 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.751202490 |
|
|
Sep 11 05:36:49 AM UTC 24 |
Sep 11 05:37:03 AM UTC 24 |
367133085 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.3070038951 |
|
|
Sep 11 05:34:46 AM UTC 24 |
Sep 11 05:37:07 AM UTC 24 |
2114965724 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.58492510 |
|
|
Sep 11 05:37:04 AM UTC 24 |
Sep 11 05:37:12 AM UTC 24 |
381616631 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.75033562 |
|
|
Sep 11 05:36:54 AM UTC 24 |
Sep 11 05:37:13 AM UTC 24 |
848576208 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.4102244154 |
|
|
Sep 11 05:34:06 AM UTC 24 |
Sep 11 05:37:14 AM UTC 24 |
18696018829 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.1800292620 |
|
|
Sep 11 05:34:18 AM UTC 24 |
Sep 11 05:37:16 AM UTC 24 |
3305637392 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.3339496715 |
|
|
Sep 11 05:37:28 AM UTC 24 |
Sep 11 05:39:08 AM UTC 24 |
1855671558 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1968013189 |
|
|
Sep 11 05:37:12 AM UTC 24 |
Sep 11 05:37:17 AM UTC 24 |
6281902881 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.956153627 |
|
|
Sep 11 05:35:40 AM UTC 24 |
Sep 11 05:37:18 AM UTC 24 |
30530145371 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2830278498 |
|
|
Sep 11 05:37:15 AM UTC 24 |
Sep 11 05:37:19 AM UTC 24 |
438784396 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.511139177 |
|
|
Sep 11 05:35:22 AM UTC 24 |
Sep 11 05:37:19 AM UTC 24 |
1826828378 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.2140253332 |
|
|
Sep 11 05:37:08 AM UTC 24 |
Sep 11 05:37:19 AM UTC 24 |
5173433575 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.4189940698 |
|
|
Sep 11 05:37:18 AM UTC 24 |
Sep 11 05:37:20 AM UTC 24 |
272260113 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.1277917922 |
|
|
Sep 11 05:37:10 AM UTC 24 |
Sep 11 05:37:21 AM UTC 24 |
5231022915 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.4270200382 |
|
|
Sep 11 05:36:45 AM UTC 24 |
Sep 11 05:37:22 AM UTC 24 |
8128537344 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1750103398 |
|
|
Sep 11 05:37:14 AM UTC 24 |
Sep 11 05:37:25 AM UTC 24 |
1164132889 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1297001074 |
|
|
Sep 11 05:37:22 AM UTC 24 |
Sep 11 05:37:25 AM UTC 24 |
594093473 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/42.i2c_host_stress_all.1623661482 |
|
|
Sep 11 05:33:53 AM UTC 24 |
Sep 11 05:37:26 AM UTC 24 |
42873079131 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.3520545714 |
|
|
Sep 11 05:37:21 AM UTC 24 |
Sep 11 05:37:26 AM UTC 24 |
343638466 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3256070414 |
|
|
Sep 11 05:37:26 AM UTC 24 |
Sep 11 05:37:30 AM UTC 24 |
2037704758 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.4260616907 |
|
|
Sep 11 05:37:26 AM UTC 24 |
Sep 11 05:37:30 AM UTC 24 |
8550971541 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2111576964 |
|
|
Sep 11 05:38:40 AM UTC 24 |
Sep 11 05:38:46 AM UTC 24 |
519682808 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.348332885 |
|
|
Sep 11 05:37:26 AM UTC 24 |
Sep 11 05:37:31 AM UTC 24 |
452524047 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.1223493206 |
|
|
Sep 11 05:36:01 AM UTC 24 |
Sep 11 05:37:31 AM UTC 24 |
12327228636 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_override.913873667 |
|
|
Sep 11 05:37:29 AM UTC 24 |
Sep 11 05:37:32 AM UTC 24 |
16388260 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2703176638 |
|
|
Sep 11 05:37:20 AM UTC 24 |
Sep 11 05:37:33 AM UTC 24 |
1100654059 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3450641375 |
|
|
Sep 11 05:37:30 AM UTC 24 |
Sep 11 05:37:33 AM UTC 24 |
251771586 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.3429130893 |
|
|
Sep 11 05:37:33 AM UTC 24 |
Sep 11 05:37:36 AM UTC 24 |
64047062 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.318034593 |
|
|
Sep 11 05:37:30 AM UTC 24 |
Sep 11 05:37:38 AM UTC 24 |
182656008 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.1813993436 |
|
|
Sep 11 05:37:32 AM UTC 24 |
Sep 11 05:37:38 AM UTC 24 |
910063945 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.2780882820 |
|
|
Sep 11 05:37:34 AM UTC 24 |
Sep 11 05:37:38 AM UTC 24 |
71868646 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.246531862 |
|
|
Sep 11 05:37:24 AM UTC 24 |
Sep 11 05:37:39 AM UTC 24 |
999173392 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_perf.3659718284 |
|
|
Sep 11 05:34:49 AM UTC 24 |
Sep 11 05:38:51 AM UTC 24 |
12080460470 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.207494317 |
|
|
Sep 11 05:36:59 AM UTC 24 |
Sep 11 05:37:39 AM UTC 24 |
9298015442 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1324513530 |
|
|
Sep 11 05:36:54 AM UTC 24 |
Sep 11 05:37:44 AM UTC 24 |
2610356491 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2414989377 |
|
|
Sep 11 05:37:40 AM UTC 24 |
Sep 11 05:37:47 AM UTC 24 |
8474790589 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1785174887 |
|
|
Sep 11 05:36:17 AM UTC 24 |
Sep 11 05:37:49 AM UTC 24 |
2147145958 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.754947929 |
|
|
Sep 11 05:37:40 AM UTC 24 |
Sep 11 05:37:49 AM UTC 24 |
1554607324 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1087594151 |
|
|
Sep 11 05:37:50 AM UTC 24 |
Sep 11 05:37:52 AM UTC 24 |
199590724 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.846687997 |
|
|
Sep 11 05:37:50 AM UTC 24 |
Sep 11 05:37:53 AM UTC 24 |
142035617 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.475612459 |
|
|
Sep 11 05:37:34 AM UTC 24 |
Sep 11 05:37:53 AM UTC 24 |
3655891972 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/35.i2c_host_perf.285564991 |
|
|
Sep 11 05:29:00 AM UTC 24 |
Sep 11 05:37:53 AM UTC 24 |
49278244089 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1658727674 |
|
|
Sep 11 05:36:51 AM UTC 24 |
Sep 11 05:37:55 AM UTC 24 |
6784633834 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3065539709 |
|
|
Sep 11 05:36:46 AM UTC 24 |
Sep 11 05:37:56 AM UTC 24 |
3058874350 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_perf.781470270 |
|
|
Sep 11 05:37:51 AM UTC 24 |
Sep 11 05:37:58 AM UTC 24 |
606555195 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.1898723598 |
|
|
Sep 11 05:37:54 AM UTC 24 |
Sep 11 05:37:58 AM UTC 24 |
1435386763 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_perf.3097923803 |
|
|
Sep 11 05:37:32 AM UTC 24 |
Sep 11 05:37:59 AM UTC 24 |
2948707308 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.2101488889 |
|
|
Sep 11 05:37:54 AM UTC 24 |
Sep 11 05:37:59 AM UTC 24 |
165029247 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.2788092536 |
|
|
Sep 11 05:37:45 AM UTC 24 |
Sep 11 05:38:01 AM UTC 24 |
5884409900 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2359980643 |
|
|
Sep 11 05:37:53 AM UTC 24 |
Sep 11 05:38:01 AM UTC 24 |
914103994 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/34.i2c_host_stress_all.2547676760 |
|
|
Sep 11 05:28:13 AM UTC 24 |
Sep 11 05:38:53 AM UTC 24 |
57275040538 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2687268464 |
|
|
Sep 11 05:37:58 AM UTC 24 |
Sep 11 05:38:01 AM UTC 24 |
125618255 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1236241557 |
|
|
Sep 11 05:37:56 AM UTC 24 |
Sep 11 05:38:01 AM UTC 24 |
1000122568 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.1682651278 |
|
|
Sep 11 05:38:00 AM UTC 24 |
Sep 11 05:38:03 AM UTC 24 |
96203451 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.1705523666 |
|
|
Sep 11 05:37:57 AM UTC 24 |
Sep 11 05:38:03 AM UTC 24 |
1115137189 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.681736932 |
|
|
Sep 11 05:38:00 AM UTC 24 |
Sep 11 05:38:04 AM UTC 24 |
494418263 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3497779792 |
|
|
Sep 11 05:38:02 AM UTC 24 |
Sep 11 05:38:04 AM UTC 24 |
17645296 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_override.3356141098 |
|
|
Sep 11 05:38:02 AM UTC 24 |
Sep 11 05:38:04 AM UTC 24 |
48575978 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.743323907 |
|
|
Sep 11 05:38:00 AM UTC 24 |
Sep 11 05:38:05 AM UTC 24 |
505471136 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2542674183 |
|
|
Sep 11 05:38:01 AM UTC 24 |
Sep 11 05:38:05 AM UTC 24 |
515329484 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.3938360238 |
|
|
Sep 11 05:31:24 AM UTC 24 |
Sep 11 05:38:59 AM UTC 24 |
33364068357 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.4230721168 |
|
|
Sep 11 05:38:04 AM UTC 24 |
Sep 11 05:38:07 AM UTC 24 |
186198150 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.2000949594 |
|
|
Sep 11 05:38:07 AM UTC 24 |
Sep 11 05:38:10 AM UTC 24 |
143348233 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.3936006226 |
|
|
Sep 11 05:38:04 AM UTC 24 |
Sep 11 05:38:14 AM UTC 24 |
173099323 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.3562157649 |
|
|
Sep 11 05:36:12 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
41441418485 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2568661940 |
|
|
Sep 11 05:38:06 AM UTC 24 |
Sep 11 05:38:16 AM UTC 24 |
783735949 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.4221607146 |
|
|
Sep 11 05:36:29 AM UTC 24 |
Sep 11 05:38:18 AM UTC 24 |
53952820871 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.1976072361 |
|
|
Sep 11 05:38:11 AM UTC 24 |
Sep 11 05:38:21 AM UTC 24 |
301242676 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.3360878136 |
|
|
Sep 11 05:37:39 AM UTC 24 |
Sep 11 05:38:23 AM UTC 24 |
2857192644 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.3714294625 |
|
|
Sep 11 05:38:22 AM UTC 24 |
Sep 11 05:38:25 AM UTC 24 |
330995280 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.2356269511 |
|
|
Sep 11 05:36:01 AM UTC 24 |
Sep 11 05:38:28 AM UTC 24 |
7547180941 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3913489447 |
|
|
Sep 11 05:38:08 AM UTC 24 |
Sep 11 05:38:29 AM UTC 24 |
967313491 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.368227277 |
|
|
Sep 11 05:36:04 AM UTC 24 |
Sep 11 05:38:29 AM UTC 24 |
10168952605 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2123120875 |
|
|
Sep 11 05:38:02 AM UTC 24 |
Sep 11 05:38:29 AM UTC 24 |
4351771867 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.3423788663 |
|
|
Sep 11 05:38:16 AM UTC 24 |
Sep 11 05:38:29 AM UTC 24 |
3045845151 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.296519974 |
|
|
Sep 11 05:37:38 AM UTC 24 |
Sep 11 05:38:32 AM UTC 24 |
1320144487 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.160963293 |
|
|
Sep 11 05:37:32 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
10714909981 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.3115065141 |
|
|
Sep 11 05:38:24 AM UTC 24 |
Sep 11 05:38:32 AM UTC 24 |
2586784833 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.2908624660 |
|
|
Sep 11 05:38:30 AM UTC 24 |
Sep 11 05:38:32 AM UTC 24 |
337091367 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1472967422 |
|
|
Sep 11 05:38:30 AM UTC 24 |
Sep 11 05:38:33 AM UTC 24 |
473313309 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3976317489 |
|
|
Sep 11 05:37:29 AM UTC 24 |
Sep 11 05:38:36 AM UTC 24 |
27090404277 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.24909950 |
|
|
Sep 11 05:38:33 AM UTC 24 |
Sep 11 05:38:37 AM UTC 24 |
913747980 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3177881791 |
|
|
Sep 11 05:38:04 AM UTC 24 |
Sep 11 05:39:05 AM UTC 24 |
7090596456 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_perf.4239689476 |
|
|
Sep 11 05:38:31 AM UTC 24 |
Sep 11 05:38:38 AM UTC 24 |
2281570034 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3412231681 |
|
|
Sep 11 05:38:29 AM UTC 24 |
Sep 11 05:38:39 AM UTC 24 |
1511159955 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2788481292 |
|
|
Sep 11 05:37:29 AM UTC 24 |
Sep 11 05:38:39 AM UTC 24 |
9922447622 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3645410340 |
|
|
Sep 11 05:38:19 AM UTC 24 |
Sep 11 05:38:40 AM UTC 24 |
400598219 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.840621603 |
|
|
Sep 11 05:38:33 AM UTC 24 |
Sep 11 05:38:40 AM UTC 24 |
2298493764 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.3643282720 |
|
|
Sep 11 05:34:46 AM UTC 24 |
Sep 11 05:38:41 AM UTC 24 |
15952867909 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1041522898 |
|
|
Sep 11 05:38:39 AM UTC 24 |
Sep 11 05:38:42 AM UTC 24 |
156614774 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2712401376 |
|
|
Sep 11 05:38:34 AM UTC 24 |
Sep 11 05:38:46 AM UTC 24 |
305783028 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.217982205 |
|
|
Sep 11 05:38:36 AM UTC 24 |
Sep 11 05:38:42 AM UTC 24 |
547161610 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.4235703659 |
|
|
Sep 11 05:37:39 AM UTC 24 |
Sep 11 05:38:50 AM UTC 24 |
1587620874 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1622943266 |
|
|
Sep 11 05:38:26 AM UTC 24 |
Sep 11 05:38:42 AM UTC 24 |
7102421816 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_alert_test.661081279 |
|
|
Sep 11 05:38:41 AM UTC 24 |
Sep 11 05:38:43 AM UTC 24 |
119724063 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1635143938 |
|
|
Sep 11 05:38:41 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
1481260485 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3084702764 |
|
|
Sep 11 05:38:40 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
1077954387 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2380315928 |
|
|
Sep 11 05:33:48 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
9838267759 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1822590637 |
|
|
Sep 11 05:38:40 AM UTC 24 |
Sep 11 05:38:46 AM UTC 24 |
935477409 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.2851701671 |
|
|
Sep 11 05:38:32 AM UTC 24 |
Sep 11 05:44:48 AM UTC 24 |
23733094784 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3707252649 |
|
|
Sep 11 05:23:49 AM UTC 24 |
Sep 11 05:46:38 AM UTC 24 |
50880896302 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.2975797271 |
|
|
Sep 11 05:30:26 AM UTC 24 |
Sep 11 05:46:41 AM UTC 24 |
63624979736 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1208106051 |
|
|
Sep 11 05:37:53 AM UTC 24 |
Sep 11 05:50:53 AM UTC 24 |
43519694336 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/1.i2c_host_perf.1717138628 |
|
|
Sep 11 05:10:20 AM UTC 24 |
Sep 11 05:54:50 AM UTC 24 |
49651228305 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.437006593 |
|
|
Sep 11 05:23:11 AM UTC 24 |
Sep 11 05:56:00 AM UTC 24 |
64684289450 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1582386071 |
|
|
Sep 11 05:35:34 AM UTC 24 |
Sep 11 06:03:33 AM UTC 24 |
71795898576 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3159611041 |
|
|
Sep 11 05:38:43 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
21209182 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.4265789170 |
|
|
Sep 11 05:38:43 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
17713802 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2775468006 |
|
|
Sep 11 05:38:43 AM UTC 24 |
Sep 11 05:38:45 AM UTC 24 |
194845728 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.498610049 |
|
|
Sep 11 05:38:43 AM UTC 24 |
Sep 11 05:38:47 AM UTC 24 |
79400906 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2268910427 |
|
|
Sep 11 05:38:42 AM UTC 24 |
Sep 11 05:38:48 AM UTC 24 |
473944376 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.231980249 |
|
|
Sep 11 05:38:46 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
46181754 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2889448819 |
|
|
Sep 11 05:38:46 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
67177744 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.3485269039 |
|
|
Sep 11 05:38:44 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
62846907 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.203162189 |
|
|
Sep 11 05:38:46 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
29296022 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2576952598 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
22066303 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2336861399 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
74560160 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3611171508 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:49 AM UTC 24 |
20691717 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.2954588795 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:50 AM UTC 24 |
61092957 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2993601046 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:50 AM UTC 24 |
155360528 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3191108763 |
|
|
Sep 11 05:38:48 AM UTC 24 |
Sep 11 05:38:51 AM UTC 24 |
538495983 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.2652388951 |
|
|
Sep 11 05:38:47 AM UTC 24 |
Sep 11 05:38:51 AM UTC 24 |
1100213085 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.2019871688 |
|
|
Sep 11 05:38:50 AM UTC 24 |
Sep 11 05:38:52 AM UTC 24 |
27311535 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2457728901 |
|
|
Sep 11 05:38:50 AM UTC 24 |
Sep 11 05:38:52 AM UTC 24 |
49260348 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.120889491 |
|
|
Sep 11 05:38:49 AM UTC 24 |
Sep 11 05:38:52 AM UTC 24 |
81334776 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.523055426 |
|
|
Sep 11 05:38:50 AM UTC 24 |
Sep 11 05:38:52 AM UTC 24 |
27729824 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1619837454 |
|
|
Sep 11 05:38:48 AM UTC 24 |
Sep 11 05:38:52 AM UTC 24 |
146713900 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1721686664 |
|
|
Sep 11 05:38:51 AM UTC 24 |
Sep 11 05:38:53 AM UTC 24 |
23920444 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.4287323470 |
|
|
Sep 11 05:38:50 AM UTC 24 |
Sep 11 05:38:53 AM UTC 24 |
193402583 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.202533611 |
|
|
Sep 11 05:38:50 AM UTC 24 |
Sep 11 05:38:53 AM UTC 24 |
118990354 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4213363858 |
|
|
Sep 11 05:38:51 AM UTC 24 |
Sep 11 05:38:54 AM UTC 24 |
77513588 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.248942083 |
|
|
Sep 11 05:38:52 AM UTC 24 |
Sep 11 05:38:55 AM UTC 24 |
19026246 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3370285641 |
|
|
Sep 11 05:38:51 AM UTC 24 |
Sep 11 05:38:55 AM UTC 24 |
196741037 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.619270686 |
|
|
Sep 11 05:38:52 AM UTC 24 |
Sep 11 05:38:55 AM UTC 24 |
19031946 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.1781780660 |
|
|
Sep 11 05:38:52 AM UTC 24 |
Sep 11 05:38:55 AM UTC 24 |
39455434 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.749871824 |
|
|
Sep 11 05:38:52 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
88520236 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.4004088917 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
295286393 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1686279070 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
26754876 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3533615489 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
163986369 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1022680525 |
|
|
Sep 11 05:38:52 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
362919069 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.951674016 |
|
|
Sep 11 05:38:55 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
16587120 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3590613696 |
|
|
Sep 11 05:38:51 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
1867666936 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3912152295 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:38:57 AM UTC 24 |
69255923 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2700351551 |
|
|
Sep 11 05:38:55 AM UTC 24 |
Sep 11 05:38:58 AM UTC 24 |
19622086 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.2582801531 |
|
|
Sep 11 05:38:55 AM UTC 24 |
Sep 11 05:38:58 AM UTC 24 |
19070379 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2874357849 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:38:58 AM UTC 24 |
71683175 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.838090098 |
|
|
Sep 11 05:38:56 AM UTC 24 |
Sep 11 05:38:59 AM UTC 24 |
79323987 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.1211564089 |
|
|
Sep 11 05:38:58 AM UTC 24 |
Sep 11 05:39:00 AM UTC 24 |
20245933 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3958109183 |
|
|
Sep 11 05:38:57 AM UTC 24 |
Sep 11 05:39:00 AM UTC 24 |
46525367 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3457206302 |
|
|
Sep 11 05:38:57 AM UTC 24 |
Sep 11 05:39:00 AM UTC 24 |
81846438 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.4167796598 |
|
|
Sep 11 05:38:58 AM UTC 24 |
Sep 11 05:39:00 AM UTC 24 |
38545490 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3523641654 |
|
|
Sep 11 05:38:56 AM UTC 24 |
Sep 11 05:39:00 AM UTC 24 |
76119632 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.4106207938 |
|
|
Sep 11 05:38:58 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
51511901 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.3659799249 |
|
|
Sep 11 05:39:03 AM UTC 24 |
Sep 11 05:39:06 AM UTC 24 |
138005887 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.449662260 |
|
|
Sep 11 05:38:54 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
445935190 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.546927913 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
18854980 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3257944298 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
34161967 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3736260562 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
21578084 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3427025529 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:01 AM UTC 24 |
253188563 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.50396770 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
358056146 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1316270158 |
|
|
Sep 11 05:39:00 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
22447843 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1290553455 |
|
|
Sep 11 05:38:55 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
483486193 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1669574864 |
|
|
Sep 11 05:38:59 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
256379542 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1905405600 |
|
|
Sep 11 05:39:00 AM UTC 24 |
Sep 11 05:39:02 AM UTC 24 |
113417214 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1677170993 |
|
|
Sep 11 05:39:01 AM UTC 24 |
Sep 11 05:39:03 AM UTC 24 |
33698549 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1338038692 |
|
|
Sep 11 05:39:01 AM UTC 24 |
Sep 11 05:39:03 AM UTC 24 |
70635533 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4276598771 |
|
|
Sep 11 05:39:01 AM UTC 24 |
Sep 11 05:39:04 AM UTC 24 |
26087138 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2668358100 |
|
|
Sep 11 05:39:02 AM UTC 24 |
Sep 11 05:39:04 AM UTC 24 |
221052333 ps |