Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29092685	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7561978

1

T1

8

T2

23

T3

980

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35860722	1			T1	12		T2	57		T3	1963
values[0x0]	397056	1			T1	10		T2	22		T3	10
values[0x1]	396885	1			T1	5		T2	30		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20298482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16356181

1

T1

11

T2

48

T3

1185

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	155350	1			T4	6		T5	4		T10	4
valid_sources[0x01]	147697	1			T4	9		T5	1		T9	1
valid_sources[0x02]	138379	1			T4	6		T5	2		T8	1
valid_sources[0x03]	141778	1			T4	15		T5	6		T9	1
valid_sources[0x04]	131174	1			T4	4		T5	5		T10	4
valid_sources[0x05]	141780	1			T4	10		T5	9		T7	1
valid_sources[0x06]	129107	1			T4	3		T5	2		T8	1
valid_sources[0x07]	129707	1			T4	8		T5	2		T8	2
valid_sources[0x08]	146006	1			T4	10		T5	5		T8	3
valid_sources[0x09]	155581	1			T4	9		T5	2		T8	2
valid_sources[0x0a]	136359	1			T4	3		T5	3		T10	1
valid_sources[0x0b]	139534	1			T4	3		T5	9		T8	1
valid_sources[0x0c]	142813	1			T2	4		T4	1		T5	4
valid_sources[0x0d]	140994	1			T4	14		T5	3		T7	2
valid_sources[0x0e]	153532	1			T2	3		T4	12		T5	5
valid_sources[0x0f]	130892	1			T4	8		T5	2		T8	1
valid_sources[0x10]	139036	1			T2	3		T4	14		T5	3
valid_sources[0x11]	147576	1			T2	2		T4	4		T5	3
valid_sources[0x12]	154240	1			T4	11		T5	4		T9	1
valid_sources[0x13]	146224	1			T4	6		T8	1		T46	3
valid_sources[0x14]	144923	1			T4	1		T5	4		T8	2
valid_sources[0x15]	161464	1			T4	6		T5	5		T8	1
valid_sources[0x16]	174010	1			T4	12		T5	2		T7	1
valid_sources[0x17]	133406	1			T4	6		T5	1		T10	1
valid_sources[0x18]	140412	1			T4	5		T5	3		T7	2
valid_sources[0x19]	138118	1			T4	4		T5	3		T6	4
valid_sources[0x1a]	141941	1			T4	9		T5	1		T8	2
valid_sources[0x1b]	140990	1			T2	10		T4	8		T5	7
valid_sources[0x1c]	149092	1			T4	9		T8	2		T45	3
valid_sources[0x1d]	164316	1			T4	13		T5	5		T7	2
valid_sources[0x1e]	145262	1			T4	7		T5	3		T10	2
valid_sources[0x1f]	132242	1			T4	17		T5	6		T8	3
valid_sources[0x20]	155798	1			T4	7		T5	4		T8	2
valid_sources[0x21]	144105	1			T4	6		T5	2		T9	1
valid_sources[0x22]	130220	1			T2	3		T4	12		T5	3
valid_sources[0x23]	154717	1			T4	3		T5	8		T10	2
valid_sources[0x24]	139489	1			T4	11		T5	5		T8	1
valid_sources[0x25]	141190	1			T4	3		T5	1		T8	1
valid_sources[0x26]	144011	1			T4	21		T5	3		T10	1
valid_sources[0x27]	151755	1			T4	3		T5	4		T9	2
valid_sources[0x28]	131384	1			T4	2		T5	1		T8	1
valid_sources[0x29]	140769	1			T4	5		T5	3		T7	2
valid_sources[0x2a]	149190	1			T4	6		T5	4		T9	1
valid_sources[0x2b]	347469	1			T4	13		T5	4		T10	2
valid_sources[0x2c]	131741	1			T4	19		T8	2		T10	1
valid_sources[0x2d]	133379	1			T4	6		T5	2		T10	2
valid_sources[0x2e]	145068	1			T4	5		T5	6		T8	7
valid_sources[0x2f]	121672	1			T4	17		T5	4		T10	1
valid_sources[0x30]	154873	1			T2	1		T4	4		T5	3
valid_sources[0x31]	134943	1			T4	3		T5	3		T8	3
valid_sources[0x32]	134245	1			T4	13		T5	1		T7	2
valid_sources[0x33]	127713	1			T4	3		T5	3		T46	4
valid_sources[0x34]	136783	1			T4	8		T5	4		T8	4
valid_sources[0x35]	144757	1			T4	5		T5	2		T8	2
valid_sources[0x36]	134473	1			T4	6		T5	3		T8	1
valid_sources[0x37]	130011	1			T4	6		T5	5		T8	1
valid_sources[0x38]	145164	1			T4	15		T5	3		T8	4
valid_sources[0x39]	149777	1			T2	3		T4	10		T10	3
valid_sources[0x3a]	136177	1			T4	5		T5	4		T8	1
valid_sources[0x3b]	145153	1			T4	4		T5	3		T7	1
valid_sources[0x3c]	140061	1			T4	9		T5	4		T9	1
valid_sources[0x3d]	130242	1			T4	10		T5	5		T8	3
valid_sources[0x3e]	149340	1			T4	28		T5	4		T7	2
valid_sources[0x3f]	131837	1			T4	9		T5	3		T9	1
valid_sources[0x40]	156204	1			T4	20		T5	6		T8	1
valid_sources[0x41]	142673	1			T4	19		T5	5		T8	1
valid_sources[0x42]	157865	1			T4	8		T5	3		T8	1
valid_sources[0x43]	154941	1			T4	21		T5	8		T7	1
valid_sources[0x44]	152424	1			T2	1		T4	14		T5	3
valid_sources[0x45]	154279	1			T4	5		T5	5		T8	6
valid_sources[0x46]	142207	1			T4	7		T5	3		T9	1
valid_sources[0x47]	134260	1			T4	6		T5	2		T8	2
valid_sources[0x48]	133226	1			T4	3		T5	2		T8	2
valid_sources[0x49]	144969	1			T2	2		T4	4		T5	3
valid_sources[0x4a]	155622	1			T4	7		T5	1		T8	1
valid_sources[0x4b]	130314	1			T4	19		T5	5		T8	2
valid_sources[0x4c]	137679	1			T4	11		T5	3		T8	4
valid_sources[0x4d]	149046	1			T4	17		T5	4		T8	2
valid_sources[0x4e]	151749	1			T2	1		T4	10		T5	6
valid_sources[0x4f]	122111	1			T4	7		T5	2		T7	1
valid_sources[0x50]	143462	1			T4	8		T8	3		T10	3
valid_sources[0x51]	126065	1			T3	9		T4	12		T5	5
valid_sources[0x52]	147252	1			T4	35		T5	2		T8	2
valid_sources[0x53]	133957	1			T2	2		T4	15		T5	1
valid_sources[0x54]	133340	1			T4	12		T5	5		T7	1
valid_sources[0x55]	150173	1			T4	11		T5	3		T8	1
valid_sources[0x56]	135839	1			T4	25		T5	1		T9	2
valid_sources[0x57]	126025	1			T4	4		T5	4		T8	2
valid_sources[0x58]	135759	1			T4	6		T5	7		T7	2
valid_sources[0x59]	138217	1			T2	5		T4	6		T5	3
valid_sources[0x5a]	152588	1			T4	14		T8	1		T46	3
valid_sources[0x5b]	129161	1			T4	7		T5	1		T8	4
valid_sources[0x5c]	141580	1			T4	7		T5	4		T10	2
valid_sources[0x5d]	150952	1			T4	8		T5	1		T8	2
valid_sources[0x5e]	136177	1			T4	4		T5	4		T10	3
valid_sources[0x5f]	164162	1			T4	20		T5	5		T7	1
valid_sources[0x60]	155116	1			T4	12		T5	6		T8	3
valid_sources[0x61]	146345	1			T4	11		T5	9		T7	1
valid_sources[0x62]	137981	1			T4	8		T5	3		T7	1
valid_sources[0x63]	136712	1			T4	4		T5	2		T8	2
valid_sources[0x64]	152699	1			T4	13		T5	3		T7	1
valid_sources[0x65]	155806	1			T4	14		T5	3		T7	1
valid_sources[0x66]	154140	1			T4	1		T5	7		T8	4
valid_sources[0x67]	130711	1			T4	7		T5	2		T8	1
valid_sources[0x68]	140676	1			T2	1		T4	13		T5	5
valid_sources[0x69]	143982	1			T4	9		T5	2		T8	1
valid_sources[0x6a]	154941	1			T4	8		T5	3		T10	1
valid_sources[0x6b]	128439	1			T4	12		T5	6		T45	2
valid_sources[0x6c]	143493	1			T4	9		T5	4		T7	2
valid_sources[0x6d]	137580	1			T4	20		T5	2		T8	1
valid_sources[0x6e]	140323	1			T4	15		T5	2		T8	1
valid_sources[0x6f]	138543	1			T4	14		T5	5		T46	6
valid_sources[0x70]	134841	1			T2	5		T4	7		T5	4
valid_sources[0x71]	151840	1			T2	1		T4	21		T5	4
valid_sources[0x72]	136290	1			T4	9		T5	3		T8	2
valid_sources[0x73]	139902	1			T4	5		T5	8		T8	2
valid_sources[0x74]	156301	1			T4	14		T5	6		T10	5
valid_sources[0x75]	138808	1			T2	1		T4	2		T5	5
valid_sources[0x76]	128200	1			T4	7		T5	4		T46	7
valid_sources[0x77]	140500	1			T4	11		T5	4		T8	2
valid_sources[0x78]	133582	1			T2	2		T4	12		T5	2
valid_sources[0x79]	148690	1			T4	5		T5	3		T8	1
valid_sources[0x7a]	138922	1			T2	9		T4	6		T5	1
valid_sources[0x7b]	162173	1			T4	9		T5	2		T8	2
valid_sources[0x7c]	131716	1			T4	12		T5	4		T8	1
valid_sources[0x7d]	128211	1			T4	6		T5	3		T8	1
valid_sources[0x7e]	130722	1			T4	7		T5	6		T8	5
valid_sources[0x7f]	160754	1			T4	10		T5	7		T7	2
valid_sources[0x80]	127811	1			T4	12		T5	5		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7208325

1

T1

3

T2

2

T3

969

values[0x0]

all_enables

biggest_size

209895

1

T1

4

T2

11

T3

9

values[0x1]

all_enables

biggest_size

143758

1

T1

1

T2

10

T3

2