Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.69	100.00	81.76			97.01	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	90.91	100.00	72.73			90.91	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T5 T7 T22 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T5 T7 T22 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T5 T7 T22 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T2 T3 T5 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T5 T7 T22 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T5 T7 T22 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T5 T7 T22 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T2 T3 T5 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T2 T3 T5 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T2 T3 T5 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T2 T3 T5 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153                         assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
154                         assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
155                       end else begin : gen_no_zero_extend_sram_addrs
156        1/1              assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
157        1/1              assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T6 T7 T8 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T6 T7 T8 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T6 T7 T8 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T6 T7 T8 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T6 T7 T8 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T6 T7 T8 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T6 T7 T8 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T6 T7 T8 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T6 T7 T8 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T6 T7 T8 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T6 T7 T8 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T51,T105
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T22
1	1	Covered	T2,T3,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T5,T7,T22

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T5,T7,T22
1	0	Covered	T163,T51,T164

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T163,T51,T164
1	Covered	T2,T3,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T163,T51,T164
0	1	Covered	T2,T3,T5
1	0	Covered	T5,T7,T22

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T5,T7,T22

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T5,T7,T22

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T22
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T43,T58
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T43,T58

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T43,T58

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T22
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T5,T7,T22
1	0	-	Covered	T2,T3,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	6768	6768	0	0
MinimalSramFifoDepth_A	6768	6768	0	0
NoErr_A	1560133656	1559437584	0	0
NoSramReadWhenEmpty_A	1560133656	1235838139	0	0
NoSramWriteWhenFull_A	1560133656	23446551	0	0
OupBufWreadyAfterSramRead_A	1560133656	638118	0	0
SramRvalidAfterRead_A	1560133656	638118	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6768	6768	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6768	6768	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560133656	1559437584	0	0
T1	6584	6344	0	0
T2	39060	38756	0	0
T3	57604	57356	0	0
T4	21728	21408	0	0
T5	56004	52908	0	0
T6	30128	29804	0	0
T7	80332	79984	0	0
T8	104352	104124	0	0
T9	50512	50312	0	0
T10	312656	312288	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560133656	1235838139	0	0
T1	6584	6344	0	0
T2	39060	33814	0	0
T3	57604	44724	0	0
T4	21728	21408	0	0
T5	56004	51194	0	0
T6	30128	27156	0	0
T7	80332	75320	0	0
T8	104352	87660	0	0
T9	50512	40692	0	0
T10	312656	242750	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560133656	23446551	0	0
T3	14401	5	0	0
T16	0	62257	0	0
T22	24539	0	0	0
T27	331278	108959	0	0
T28	0	142950	0	0
T34	6945	0	0	0
T35	12658	0	0	0
T39	0	147250	0	0
T47	0	1502	0	0
T50	185532	8	0	0
T51	0	24	0	0
T54	429039	0	0	0
T61	54029	28	0	0
T62	56861	1676	0	0
T63	0	4	0	0
T66	0	945	0	0
T67	4520	0	0	0
T71	60984	0	0	0
T72	128530	0	0	0
T73	16796	0	0	0
T83	504758	0	0	0
T100	0	5604	0	0
T165	0	7	0	0
T166	0	26	0	0
T167	0	847	0	0
T168	20358	4470	0	0
T169	0	108049	0	0
T170	0	43707	0	0
T171	0	98557	0	0
T172	0	85600	0	0
T173	159791	0	0	0
T174	67575	0	0	0
T175	5104	0	0	0
T176	112467	0	0	0
T177	353671	0	0	0
T178	177125	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560133656	638118	0	0
T5	14001	6	0	0
T6	15064	20	0	0
T7	40166	19	0	0
T8	52176	56	0	0
T9	25256	0	0	0
T10	156328	106	0	0
T11	0	20	0	0
T12	0	114	0	0
T14	0	1	0	0
T22	0	3	0	0
T29	0	116	0	0
T32	481549	0	0	0
T40	0	181	0	0
T41	0	69	0	0
T44	0	1	0	0
T45	96450	281	0	0
T46	266724	323	0	0
T61	0	266	0	0
T69	136411	326	0	0
T70	0	17	0	0
T71	0	136	0	0
T74	1990	0	0	0
T75	7794	0	0	0
T105	189195	806	0	0
T125	21199	0	0	0
T126	106465	0	0	0
T127	11138	0	0	0
T128	82686	0	0	0
T129	118238	0	0	0
T130	82183	0	0	0
T131	50207	0	0	0
T179	0	26	0	0
T180	67882	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560133656	638118	0	0
T5	14001	6	0	0
T6	15064	20	0	0
T7	40166	19	0	0
T8	52176	56	0	0
T9	25256	0	0	0
T10	156328	106	0	0
T11	0	20	0	0
T12	0	114	0	0
T14	0	1	0	0
T22	0	3	0	0
T29	0	116	0	0
T32	481549	0	0	0
T40	0	181	0	0
T41	0	69	0	0
T44	0	1	0	0
T45	96450	281	0	0
T46	266724	323	0	0
T61	0	266	0	0
T69	136411	326	0	0
T70	0	17	0	0
T71	0	136	0	0
T74	1990	0	0	0
T75	7794	0	0	0
T105	189195	806	0	0
T125	21199	0	0	0
T126	106465	0	0	0
T127	11138	0	0	0
T128	82686	0	0	0
T129	118238	0	0	0
T130	82183	0	0	0
T131	50207	0	0	0
T179	0	26	0	0
T180	67882	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T5 T22 T29 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T5 T22 T29 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T5 T22 T29 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T2 T5 T34 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T5 T22 T29 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T5 T22 T29 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T5 T22 T29 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T2 T5 T34 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T2 T5 T34 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T2 T5 T34 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T2 T5 T34 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T5,T34

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T22,T29
1	1	Covered	T2,T5,T34

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T34
1	1	Covered	T5,T22,T29

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T34
0	1	Covered	T5,T22,T29
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T5,T34

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T5,T34
1	0	Covered	T5,T22,T29

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T34
1	1	Covered	T5,T22,T29

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T34
1	1	Covered	T5,T22,T29

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T34
1	1	Covered	T2,T5,T34

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T34
1	1	Covered	T2,T5,T34

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T22,T29
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T34

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T34

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T168,T28
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T168,T28

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T27,T168,T28

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T22,T29
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T5,T22,T29
1	0	-	Covered	T2,T5,T34
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	390033414	389859396	0	0
NoSramReadWhenEmpty_A	390033414	329947580	0	0
NoSramWriteWhenFull_A	390033414	22819408	0	0
OupBufWreadyAfterSramRead_A	390033414	168590	0	0
SramRvalidAfterRead_A	390033414	168590	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	389859396	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	329947580	0	0
T1	1646	1586	0	0
T2	9765	4747	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	11513	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	22819408	0	0
T16	0	62257	0	0
T27	331278	108959	0	0
T28	0	142950	0	0
T39	0	147250	0	0
T54	429039	0	0	0
T83	504758	0	0	0
T100	0	5604	0	0
T168	20358	4470	0	0
T169	0	108049	0	0
T170	0	43707	0	0
T171	0	98557	0	0
T172	0	85600	0	0
T173	159791	0	0	0
T174	67575	0	0	0
T175	5104	0	0	0
T176	112467	0	0	0
T177	353671	0	0	0
T178	177125	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	168590	0	0
T5	14001	6	0	0
T6	7532	0	0	0
T7	20083	0	0	0
T8	26088	0	0	0
T9	12628	0	0	0
T10	78164	0	0	0
T11	0	20	0	0
T12	0	114	0	0
T14	0	1	0	0
T22	0	3	0	0
T29	0	116	0	0
T40	0	181	0	0
T41	0	69	0	0
T44	0	1	0	0
T45	48225	0	0	0
T46	133362	0	0	0
T74	995	0	0	0
T75	3897	0	0	0
T179	0	26	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	168590	0	0
T5	14001	6	0	0
T6	7532	0	0	0
T7	20083	0	0	0
T8	26088	0	0	0
T9	12628	0	0	0
T10	78164	0	0	0
T11	0	20	0	0
T12	0	114	0	0
T14	0	1	0	0
T22	0	3	0	0
T29	0	116	0	0
T40	0	181	0	0
T41	0	69	0	0
T44	0	1	0	0
T45	48225	0	0	0
T46	133362	0	0	0
T74	995	0	0	0
T75	3897	0	0	0
T179	0	26	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T7 T8 T9 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T7 T8 T9 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T7 T8 T9 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T7 T8 T9 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T7 T8 T9 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T7 T8 T9 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T7 T8 T9 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T7 T8 T9 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T7 T8 T9 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T7 T8 T9 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T7 T8 T9 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T59,T60
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T59,T60

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T58,T59,T60

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T8,T9
1	0	-	Covered	T7,T8,T9
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	390033414	389859396	0	0
NoSramReadWhenEmpty_A	390033414	369073689	0	0
NoSramWriteWhenFull_A	390033414	330338	0	0
OupBufWreadyAfterSramRead_A	390033414	110594	0	0
SramRvalidAfterRead_A	390033414	110594	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	389859396	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	369073689	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	18796	0	0
T8	26088	20029	0	0
T9	12628	2958	0	0
T10	78164	71288	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	330338	0	0
T12	60661	0	0	0
T40	64144	0	0	0
T47	47662	0	0	0
T58	12437	9389	0	0
T59	0	5257	0	0
T60	0	9323	0	0
T63	59248	0	0	0
T64	83948	0	0	0
T104	839	0	0	0
T181	0	6650	0	0
T182	0	14801	0	0
T183	0	6038	0	0
T184	0	12100	0	0
T185	0	294	0	0
T186	0	1954	0	0
T187	0	11478	0	0
T188	12817	0	0	0
T189	196621	0	0	0
T190	8134	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	110594	0	0
T7	20083	6	0	0
T8	26088	31	0	0
T9	12628	42	0	0
T10	78164	33	0	0
T45	48225	0	0	0
T46	133362	198	0	0
T67	0	8	0	0
T69	136411	273	0	0
T70	0	239	0	0
T71	0	248	0	0
T72	0	243	0	0
T74	995	0	0	0
T75	3897	0	0	0
T76	44336	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	110594	0	0
T7	20083	6	0	0
T8	26088	31	0	0
T9	12628	42	0	0
T10	78164	33	0	0
T45	48225	0	0	0
T46	133362	198	0	0
T67	0	8	0	0
T69	136411	273	0	0
T70	0	239	0	0
T71	0	248	0	0
T72	0	243	0	0
T74	995	0	0	0
T75	3897	0	0	0
T76	44336	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T105 T32 T83 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T105 T32 T83 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T105 T32 T83 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T3 T43 T82 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T105 T32 T83 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T105 T32 T83 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T105 T32 T83 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T3 T43 T82 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T3 T43 T82 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T3 T43 T82 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T3 T43 T82 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T105,T106,T107
1	1	Covered	T3,T5,T14

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T43,T82

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T105,T32,T83
1	1	Covered	T3,T43,T82

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T43,T82
1	1	Covered	T105,T32,T83

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T43,T82
0	1	Covered	T105,T32,T83
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T43,T82

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T43,T82
1	0	Covered	T105,T32,T83

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T43,T82
1	1	Covered	T105,T32,T83

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T43,T82
1	1	Covered	T105,T32,T83

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T43,T82
1	1	Covered	T3,T43,T82

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T43,T82
1	1	Covered	T3,T43,T82

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T105,T32,T83
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T43,T82

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T43,T82

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T43,T82
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T43,T82

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T43,T82
1	0	Not Covered
1	1	Covered	T3,T43,T82

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T105,T32,T83
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T105,T32,T83
1	0	-	Covered	T3,T43,T82
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	390033414	389859396	0	0
NoSramReadWhenEmpty_A	390033414	365820846	0	0
NoSramWriteWhenFull_A	390033414	236949	0	0
OupBufWreadyAfterSramRead_A	390033414	119412	0	0
SramRvalidAfterRead_A	390033414	119412	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	389859396	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	365820846	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	1707	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	236949	0	0
T3	14401	5	0	0
T4	5432	0	0	0
T5	14001	0	0	0
T6	7532	0	0	0
T7	20083	0	0	0
T8	26088	0	0	0
T9	12628	0	0	0
T10	78164	0	0	0
T32	0	892	0	0
T43	0	15	0	0
T45	48225	0	0	0
T46	133362	0	0	0
T82	0	7	0	0
T83	0	962	0	0
T84	0	626	0	0
T105	0	3041	0	0
T106	0	3267	0	0
T191	0	9	0	0
T192	0	4	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	119412	0	0
T32	481549	1116	0	0
T83	0	1178	0	0
T84	0	868	0	0
T94	0	1178	0	0
T101	0	1178	0	0
T105	189195	806	0	0
T106	0	930	0	0
T107	0	1240	0	0
T125	21199	0	0	0
T126	106465	0	0	0
T127	11138	0	0	0
T128	82686	0	0	0
T129	118238	0	0	0
T130	82183	0	0	0
T131	50207	0	0	0
T180	67882	0	0	0
T193	0	992	0	0
T194	0	682	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	119412	0	0
T32	481549	1116	0	0
T83	0	1178	0	0
T84	0	868	0	0
T94	0	1178	0	0
T101	0	1178	0	0
T105	189195	806	0	0
T106	0	930	0	0
T107	0	1240	0	0
T125	21199	0	0	0
T126	106465	0	0	0
T127	11138	0	0	0
T128	82686	0	0	0
T129	118238	0	0	0
T130	82183	0	0	0
T131	50207	0	0	0
T180	67882	0	0	0
T193	0	992	0	0
T194	0	682	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153                         assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
154                         assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
155                       end else begin : gen_no_zero_extend_sram_addrs
156        1/1              assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
157        1/1              assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T6 T7 T8 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T6 T7 T8 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T6 T7 T8 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T6 T7 T8 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T6 T7 T8 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T6 T7 T8 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T6 T7 T8 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T6 T7 T8 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T6 T7 T8 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T6 T7 T8 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T6 T7 T8 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T51
1	1	Covered	T6,T7,T8

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T163,T51,T164

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T163,T51,T164
1	Covered	T6,T7,T8

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T163,T51,T164
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T61,T62,T50
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T61,T62,T50

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T61,T62,T50

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6,T7,T8
1	0	-	Covered	T6,T7,T8
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1692	1692	0	0
MinimalSramFifoDepth_A	1692	1692	0	0
NoErr_A	390033414	389859396	0	0
NoSramReadWhenEmpty_A	390033414	170996024	0	0
NoSramWriteWhenFull_A	390033414	59856	0	0
OupBufWreadyAfterSramRead_A	390033414	239522	0	0
SramRvalidAfterRead_A	390033414	239522	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	389859396	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	170996024	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	4803	0	0
T7	20083	16532	0	0
T8	26088	15569	0	0
T9	12628	12578	0	0
T10	78164	15318	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	59856	0	0
T22	24539	0	0	0
T34	6945	0	0	0
T35	12658	0	0	0
T47	0	1502	0	0
T50	185532	8	0	0
T51	0	24	0	0
T61	54029	28	0	0
T62	56861	1676	0	0
T63	0	4	0	0
T66	0	945	0	0
T67	4520	0	0	0
T71	60984	0	0	0
T72	128530	0	0	0
T73	16796	0	0	0
T165	0	7	0	0
T166	0	26	0	0
T167	0	847	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	239522	0	0
T6	7532	20	0	0
T7	20083	19	0	0
T8	26088	56	0	0
T9	12628	0	0	0
T10	78164	106	0	0
T45	48225	281	0	0
T46	133362	323	0	0
T61	0	266	0	0
T69	136411	326	0	0
T70	0	17	0	0
T71	0	136	0	0
T74	995	0	0	0
T75	3897	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	239522	0	0
T6	7532	20	0	0
T7	20083	19	0	0
T8	26088	56	0	0
T9	12628	0	0	0
T10	78164	106	0	0
T45	48225	281	0	0
T46	133362	323	0	0
T61	0	266	0	0
T69	136411	326	0	0
T70	0	17	0	0
T71	0	136	0	0
T74	995	0	0	0
T75	3897	0	0	0