Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.i2c_core.intr_hw_fmt_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_rx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_acq_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_rx_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_controller_halt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_scl_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_sda_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_stretch_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_sda_unstable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_cmd_complete

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_tx_stretch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_tx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_acq_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_unexp_stop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_host_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT3,T4,T5

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T29,T14
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T29,T14
10CoveredT5,T29,T14

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T13
11CoveredT5,T29,T14

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 25380 25380 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25380 25380 0 0
T1 15 15 0 0
T2 15 15 0 0
T3 15 15 0 0
T4 15 15 0 0
T5 15 15 0 0
T6 15 15 0 0
T7 15 15 0 0
T8 15 15 0 0
T9 15 15 0 0
T10 15 15 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T43,T40

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T43,T40

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT3,T43,T40

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT8,T10,T45

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT8,T10,T45

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT76,T61,T62
11CoveredT8,T10,T45

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT105,T106,T107
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT105,T106,T107
10CoveredT105,T106,T107

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T240
11CoveredT105,T106,T107

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T240
10CoveredT5,T14,T11

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T240
10CoveredT5,T14,T11

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T240
11CoveredT5,T14,T11

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT5,T14,T18

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT5,T14,T18

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT5,T14,T18

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT5,T14,T18

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T29,T14
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T29,T14
10CoveredT5,T29,T14

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T13
11CoveredT5,T29,T14

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T14,T18
10CoveredT5,T14,T18

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT5,T14,T18

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT122,T199,T240

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T240

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT3,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T240
11CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T240
10CoveredT7,T8,T9

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T240
10CoveredT7,T8,T9

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T240
11CoveredT7,T8,T9

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT3,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  | T122 T199 T78  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT6,T7,T10

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T199,T78
10CoveredT6,T7,T10

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT6,T7,T10

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T199,T78
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT50,T51
10CoveredT122,T199,T240

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T240

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT50,T51,T122
10CoveredT50,T51,T122

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T240
11CoveredT50,T51,T122

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT69,T72,T77
10CoveredT122,T199,T78

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT122,T199,T78

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT69,T72,T77
10CoveredT69,T72,T77

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT122,T199,T78
11CoveredT69,T72,T77

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1692 1692 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1692 1692 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%