Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T3,T4,T5 |
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T29,T14 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T29,T14 |
1 | 0 | Covered | T5,T29,T14 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T5,T29,T14 |
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_intr_hw
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
25380 |
25380 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25380 |
25380 |
0 |
0 |
T1 |
15 |
15 |
0 |
0 |
T2 |
15 |
15 |
0 |
0 |
T3 |
15 |
15 |
0 |
0 |
T4 |
15 |
15 |
0 |
0 |
T5 |
15 |
15 |
0 |
0 |
T6 |
15 |
15 |
0 |
0 |
T7 |
15 |
15 |
0 |
0 |
T8 |
15 |
15 |
0 |
0 |
T9 |
15 |
15 |
0 |
0 |
T10 |
15 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T3,T4,T5 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T43,T40 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T43,T40 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T3,T43,T40 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T8,T10,T45 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T8,T10,T45 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T76,T61,T62 |
1 | 1 | Covered | T8,T10,T45 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T105,T106,T107 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T105,T106,T107 |
1 | 0 | Covered | T105,T106,T107 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T240 |
1 | 1 | Covered | T105,T106,T107 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T240 |
1 | 0 | Covered | T5,T14,T11 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T240 |
1 | 0 | Covered | T5,T14,T11 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T240 |
1 | 1 | Covered | T5,T14,T11 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T5,T14,T18 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T5,T14,T18 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T5,T14,T18 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T5,T14,T18 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T29,T14 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T29,T14 |
1 | 0 | Covered | T5,T29,T14 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T5,T29,T14 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T14,T18 |
1 | 0 | Covered | T5,T14,T18 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T5,T14,T18 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T122,T199,T240 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T240 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T240 |
1 | 1 | Covered | T3,T4,T5 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T240 |
1 | 0 | Covered | T7,T8,T9 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T240 |
1 | 0 | Covered | T7,T8,T9 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T240 |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T3,T4,T5 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 2/2 if (!rst_ni) test_q <= '0;
Tests: T1 T2 T3 | T1 T2 T3
76 2/2 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
Tests: T1 T2 T3 | T122 T199 T78
MISSING_ELSE
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
Tests: T1 T2 T3
82
83 1/1 assign status = event_intr_i | test_q;
Tests: T1 T2 T3
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
Tests: T1 T2 T3
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T6,T7,T10 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T122,T199,T78 |
1 | 0 | Covered | T6,T7,T10 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T6,T7,T10 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
75 if (!rst_ni) test_q <= '0;
-1-
==>
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T122,T199,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T50,T51 |
1 | 0 | Covered | T122,T199,T240 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T240 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T50,T51,T122 |
1 | 0 | Covered | T50,T51,T122 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T240 |
1 | 1 | Covered | T50,T51,T122 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
61 logic [Width-1:0] new_event;
62 1/1 assign new_event =
Tests: T1 T2 T3
63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64 1/1 assign hw2reg_intr_state_de_o = |new_event;
Tests: T1 T2 T3
65 // for scalar interrupts, this resolves to '1' with new event
66 // for vector interrupts, new events are OR'd in to existing interrupt state
67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
Tests: T1 T2 T3
68
69 1/1 assign status = reg2hw_intr_state_q_i ;
Tests: T1 T2 T3
70 end : g_intr_event
71 else if (IntrT == "Status") begin : g_intr_status
72 logic [Width-1:0] test_q; // Storing test. Cleared by SW
73
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 if (!rst_ni) test_q <= '0;
76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77 end
78
79 // TODO: In Status type, INTR_STATE is better to be external type and RO.
80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81 assign hw2reg_intr_state_d_o = event_intr_i | test_q;
82
83 assign status = event_intr_i | test_q;
84
85 // To make the timing same to event type, status signal does not use CSR.q,
86 // rather the input of the CSR.
87 logic unused_reg2hw;
88 assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89 end : g_intr_status
90
91
92 if (FlopOutput == 1) begin : gen_flop_intr_output
93 // flop the interrupt output
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 intr_o <= '0;
Tests: T1 T2 T3
97 end else begin
98 1/1 intr_o <= status & reg2hw_intr_enable_q_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T69,T72,T77 |
1 | 0 | Covered | T122,T199,T78 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T122,T199,T78 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T69,T72,T77 |
1 | 0 | Covered | T69,T72,T77 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T122,T199,T78 |
1 | 1 | Covered | T69,T72,T77 |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
95 if (!rst_ni) begin
-1-
96 intr_o <= '0;
==>
97 end else begin
98 intr_o <= status & reg2hw_intr_enable_q_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1692 |
1692 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1692 |
1692 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |