Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390750892	0	0	0
ctrl_rd_A	390750892	2643	0	0
host_fifo_config_rd_A	390750892	5610	0	0
host_nack_handler_timeout_rd_A	390750892	1818	0	0
host_timeout_ctrl_rd_A	390750892	1778	0	0
intr_enable_rd_A	390750892	4353	0	0
ovrd_rd_A	390750892	1958	0	0
target_fifo_config_rd_A	390750892	1973	0	0
target_id_rd_A	390750892	2299	0	0
target_timeout_ctrl_rd_A	390750892	1907	0	0
timeout_ctrl_rd_A	390750892	2331	0	0
timing0_rd_A	390750892	2046	0	0
timing1_rd_A	390750892	2037	0	0
timing2_rd_A	390750892	1893	0	0
timing3_rd_A	390750892	1796	0	0
timing4_rd_A	390750892	2006	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2643	0	0
T108	7234	101	0	0
T109	3133	7	0	0
T110	3450	34	0	0
T111	23972	103	0	0
T112	8571	85	0	0
T113	5796	52	0	0
T114	2463	23	0	0
T115	12374	21	0	0
T116	12954	135	0	0
T117	5899	73	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	5610	0	0
T32	481549	232	0	0
T83	0	207	0	0
T84	0	194	0	0
T118	0	102	0	0
T119	0	145	0	0
T120	0	99	0	0
T121	0	78	0	0
T122	0	191	0	0
T123	0	184	0	0
T124	0	172	0	0
T125	21199	0	0	0
T126	106465	0	0	0
T127	11138	0	0	0
T128	82686	0	0	0
T129	118238	0	0	0
T130	82183	0	0	0
T131	50207	0	0	0
T132	1323	0	0	0
T133	3908	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1818	0	0
T108	7234	66	0	0
T109	3133	21	0	0
T110	3450	20	0	0
T111	23972	122	0	0
T112	8571	28	0	0
T113	5796	33	0	0
T114	2463	5	0	0
T115	12374	12	0	0
T116	12954	56	0	0
T117	5899	18	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1778	0	0
T108	7234	21	0	0
T109	3133	13	0	0
T110	3450	31	0	0
T111	23972	137	0	0
T112	8571	30	0	0
T113	5796	25	0	0
T115	12374	48	0	0
T116	12954	44	0	0
T117	5899	28	0	0
T134	3206	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	4353	0	0
T20	0	19	0	0
T78	0	7	0	0
T108	0	170	0	0
T109	0	65	0	0
T110	0	30	0	0
T111	0	153	0	0
T112	0	108	0	0
T122	100575	47	0	0
T135	0	20	0	0
T136	0	11	0	0
T137	80896	0	0	0
T138	75518	0	0	0
T139	62271	0	0	0
T140	24059	0	0	0
T141	108855	0	0	0
T142	305716	0	0	0
T143	96950	0	0	0
T144	37466	0	0	0
T145	167801	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1958	0	0
T28	329332	0	0	0
T33	173598	0	0	0
T146	2323	60	0	0
T147	0	67	0	0
T148	0	63	0	0
T149	0	39	0	0
T150	0	46	0	0
T151	0	63	0	0
T152	0	29	0	0
T153	0	35	0	0
T154	0	61	0	0
T155	0	29	0	0
T156	43231	0	0	0
T157	79101	0	0	0
T158	45636	0	0	0
T159	40955	0	0	0
T160	6392	0	0	0
T161	22470	0	0	0
T162	720390	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1973	0	0
T108	7234	38	0	0
T109	3133	4	0	0
T110	3450	3	0	0
T111	23972	161	0	0
T112	8571	38	0	0
T113	5796	30	0	0
T114	2463	9	0	0
T115	12374	43	0	0
T116	12954	54	0	0
T117	5899	26	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2299	0	0
T108	7234	59	0	0
T109	3133	11	0	0
T110	3450	29	0	0
T111	23972	142	0	0
T112	8571	40	0	0
T113	5796	102	0	0
T114	2463	14	0	0
T115	12374	14	0	0
T116	12954	71	0	0
T117	5899	43	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1907	0	0
T108	7234	34	0	0
T109	3133	7	0	0
T110	3450	12	0	0
T111	23972	100	0	0
T112	8571	30	0	0
T113	5796	47	0	0
T114	2463	21	0	0
T115	12374	37	0	0
T116	12954	99	0	0
T117	5899	37	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2331	0	0
T108	7234	51	0	0
T109	3133	15	0	0
T110	3450	31	0	0
T111	23972	153	0	0
T112	8571	52	0	0
T113	5796	37	0	0
T114	2463	21	0	0
T115	12374	39	0	0
T116	12954	110	0	0
T117	5899	29	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2046	0	0
T108	7234	18	0	0
T109	3133	8	0	0
T110	3450	20	0	0
T111	23972	158	0	0
T112	8571	40	0	0
T113	5796	57	0	0
T114	2463	9	0	0
T115	12374	37	0	0
T116	12954	82	0	0
T117	5899	63	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2037	0	0
T108	7234	20	0	0
T109	3133	19	0	0
T110	3450	20	0	0
T111	23972	117	0	0
T112	8571	40	0	0
T113	5796	13	0	0
T114	2463	22	0	0
T115	12374	43	0	0
T116	12954	85	0	0
T117	5899	88	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1893	0	0
T108	7234	30	0	0
T109	3133	9	0	0
T110	3450	12	0	0
T111	23972	172	0	0
T112	8571	60	0	0
T113	5796	1	0	0
T114	2463	15	0	0
T115	12374	32	0	0
T116	12954	54	0	0
T117	5899	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	1796	0	0
T108	7234	43	0	0
T109	3133	9	0	0
T110	3450	38	0	0
T111	23972	130	0	0
T112	8571	20	0	0
T113	5796	26	0	0
T114	2463	7	0	0
T115	12374	13	0	0
T116	12954	39	0	0
T117	5899	24	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390750892	2006	0	0
T108	7234	25	0	0
T109	3133	7	0	0
T110	3450	41	0	0
T111	23972	169	0	0
T112	8571	14	0	0
T113	5796	65	0	0
T114	2463	8	0	0
T115	12374	38	0	0
T116	12954	49	0	0
T117	5899	42	0	0