Unified Coverage Report :: Module :: i2c_target_fsm

Module : i2c_target_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.20	93.80	80.00		73.58	83.64	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_target_fsm	86.20	93.80	80.00		73.58	83.64	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.20	93.80	80.00		73.58	83.64	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.20	93.80	80.00		73.58	83.64	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.58	97.74	79.23			93.33	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
TOTAL		355	333	93.80
ALWAYS	130	8	7	87.50
ALWAYS	144	3	3	100.00
ALWAYS	154	6	6	100.00
ALWAYS	165	5	5	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	182	3	3	100.00
ALWAYS	191	3	3	100.00
ALWAYS	200	7	7	100.00
CONT_ASSIGN	212	1	1	100.00
ALWAYS	216	9	9	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	239	7	7	100.00
ALWAYS	250	5	5	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
ALWAYS	302	4	4	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	331	148	139	93.92
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
ALWAYS	674	119	107	89.92
ALWAYS	1007	3	3	100.00
ALWAYS	1016	3	3	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1027	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : i2c_target_fsm

	Total	Covered	Percent
Conditions	120	96	80.00
Logical	120	96	80.00
Non-Logical	0	0
Event	0	0

 LINE       158
 EXPRESSION (start_detect_i && target_idle_o)
             -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T3,T5

 LINE       167
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Not Covered
1	1	Covered	T6,T7,T10

 LINE       175
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Covered	T6,T7,T10
1	0	Covered	T1,T2,T3

 LINE       212
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       220
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T6,T7,T8

 LINE       231
 EXPRESSION (((input_byte[7:1] & target_mask0_i) == target_address0_i) && (target_mask0_i != '0))
             ----------------------------1----------------------------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       231
 SUB-EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
                ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (target_mask0_i != '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       233
 EXPRESSION (((input_byte[7:1] & target_mask1_i) == target_address1_i) && (target_mask1_i != '0))
             ----------------------------1----------------------------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       233
 SUB-EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
                ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       233
 SUB-EXPRESSION (target_mask1_i != '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       235
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       243
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       252
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       304
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T6,T7,T8

 LINE       323
 EXPRESSION (target_enable_i & xfer_for_us_q & rw_bit_q & stop_detect_i & ((!expect_stop)))
             -------1-------   ------2------   ----3---   ------4------   --------5-------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T50,T58,T51
1	1	0	1	1	Covered	T6,T8,T10
1	1	1	0	1	Covered	T7,T8,T9
1	1	1	1	0	Covered	T7,T8,T9
1	1	1	1	1	Covered	T50,T51

 LINE       327
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T61,T62,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T61,T62,T58

 LINE       416
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       508
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       589
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Not Covered
1	0	Covered	T61,T62,T63

 LINE       589
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Not Covered
1	1	Not Covered

 LINE       623
 EXPRESSION (target_enable_i && (stop_detect_i || bus_timeout_i))
             -------1-------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       623
 SUB-EXPRESSION (stop_detect_i || bus_timeout_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       625
 EXPRESSION (bus_timeout_i && rw_bit_q)
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       631
 EXPRESSION (nack_transaction_q || bus_timeout_i)
             ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Not Covered
1	0	Covered	T61,T62,T58

 LINE       636
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       646
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T45,T61,T62

 LINE       651
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T61,T62,T58
1	1	Covered	T61,T62,T58

 LINE       665
 EXPRESSION (((!tx_fifo_rvalid_i)) || unhandled_tx_stretch_event_i || (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------    --------------2-------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T7,T8,T9
0	0	1	Covered	T8,T9,T46
0	1	0	Covered	T67,T68,T58
1	0	0	Covered	T1,T2,T3

 LINE       718
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       757
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       808
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T7,T8,T9

 LINE       856
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       883
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T7,T8

 LINE       903
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       920
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T52,T54,T55
1	Not Covered

 LINE       946
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       958
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Not Covered
1	0	Covered	T61,T62,T63

 LINE       958
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Not Covered
1	1	Not Covered

 LINE       969
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T6,T7,T10

 LINE       986
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Not Covered

 LINE       996
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       998
 EXPRESSION (stop_detect_i || bus_timeout_i)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : i2c_target_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	26	25	96.15	(Not included in score)
Transitions	106	78	73.58
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	876	Covered	T6,T7,T8
AcquireAckPulse	871	Covered	T6,T7,T8
AcquireAckSetup	865	Covered	T6,T7,T8
AcquireAckWait	846	Covered	T6,T7,T8
AcquireByte	782	Covered	T6,T7,T8
AcquireStart	997	Covered	T6,T7,T8
AddrAckHold	750	Covered	T6,T7,T8
AddrAckPulse	745	Covered	T6,T7,T8
AddrAckSetup	721	Covered	T6,T7,T8
AddrAckWait	703	Covered	T6,T7,T8
AddrRead	693	Covered	T6,T7,T8
Idle	995	Covered	T1,T2,T3
StretchAcqFull	863	Covered	T6,T7,T10
StretchAcqSetup	961	Covered	T6,T7,T10
StretchAddr	776	Covered	T50,T51,T52
StretchAddrAck	734	Covered	T47,T48,T49
StretchAddrAckSetup	895	Not Covered
StretchTx	789	Covered	T7,T8,T9
StretchTxSetup	936	Covered	T7,T8,T9
TransmitAck	810	Covered	T7,T8,T9
TransmitAckPulse	821	Covered	T7,T8,T9
TransmitHold	801	Covered	T7,T8,T9
TransmitPulse	796	Covered	T7,T8,T9
TransmitSetup	791	Covered	T7,T8,T9
TransmitWait	779	Covered	T7,T8,T9
WaitForStop	709	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	884	Covered	T6,T7,T8
AcquireAckHold->AcquireStart	997	Covered	T50,T51
AcquireAckHold->Idle	995	Covered	T50,T51
AcquireAckHold->WaitForStop	1001	Not Covered
AcquireAckPulse->AcquireAckHold	876	Covered	T6,T7,T8
AcquireAckPulse->AcquireStart	997	Covered	T50,T51
AcquireAckPulse->Idle	995	Covered	T50,T51
AcquireAckPulse->WaitForStop	1001	Not Covered
AcquireAckSetup->AcquireAckPulse	871	Covered	T6,T7,T8
AcquireAckSetup->AcquireStart	997	Covered	T50,T51
AcquireAckSetup->Idle	995	Covered	T50,T51
AcquireAckSetup->WaitForStop	1001	Not Covered
AcquireAckWait->AcquireAckSetup	865	Covered	T6,T7,T8
AcquireAckWait->AcquireStart	997	Covered	T50,T51
AcquireAckWait->Idle	995	Covered	T50,T51
AcquireAckWait->StretchAcqFull	863	Covered	T6,T7,T10
AcquireAckWait->WaitForStop	855	Not Covered
AcquireByte->AcquireAckWait	846	Covered	T6,T7,T8
AcquireByte->AcquireStart	997	Covered	T7,T8,T10
AcquireByte->Idle	995	Covered	T6,T8,T10
AcquireByte->WaitForStop	1001	Not Covered
AcquireStart->AddrRead	693	Covered	T6,T7,T8
AcquireStart->Idle	995	Covered	T50,T51
AcquireStart->WaitForStop	1001	Not Covered
AddrAckHold->AcquireByte	782	Covered	T6,T7,T8
AddrAckHold->AcquireStart	997	Covered	T50,T51
AddrAckHold->Idle	995	Covered	T50,T51
AddrAckHold->StretchAddr	776	Covered	T50,T51,T52
AddrAckHold->TransmitWait	779	Covered	T7,T8,T9
AddrAckHold->WaitForStop	769	Not Covered
AddrAckPulse->AcquireStart	997	Covered	T50,T51
AddrAckPulse->AddrAckHold	750	Covered	T6,T7,T8
AddrAckPulse->Idle	995	Covered	T50,T51
AddrAckPulse->WaitForStop	1001	Not Covered
AddrAckSetup->AcquireStart	997	Covered	T50,T51
AddrAckSetup->AddrAckPulse	745	Covered	T6,T7,T8
AddrAckSetup->Idle	995	Covered	T50,T51
AddrAckSetup->WaitForStop	1001	Not Covered
AddrAckWait->AcquireStart	997	Covered	T50,T51
AddrAckWait->AddrAckSetup	721	Covered	T6,T7,T8
AddrAckWait->Idle	995	Covered	T50,T51
AddrAckWait->StretchAddrAck	734	Covered	T47,T48,T49
AddrAckWait->WaitForStop	717	Not Covered
AddrRead->AcquireStart	997	Covered	T50,T51
AddrRead->AddrAckWait	703	Covered	T6,T7,T8
AddrRead->Idle	995	Covered	T50,T58,T51
AddrRead->WaitForStop	709	Covered	T10,T64,T65
Idle->AcquireStart	997	Covered	T6,T7,T8
Idle->WaitForStop	1001	Not Covered
StretchAcqFull->AcquireStart	997	Covered	T50,T51
StretchAcqFull->Idle	995	Covered	T50,T51
StretchAcqFull->StretchAcqSetup	961	Covered	T6,T7,T10
StretchAcqFull->WaitForStop	959	Covered	T61,T62,T63
StretchAcqSetup->AcquireAckSetup	970	Covered	T6,T7,T10
StretchAcqSetup->AcquireStart	997	Not Covered
StretchAcqSetup->Idle	995	Not Covered
StretchAcqSetup->WaitForStop	1001	Not Covered
StretchAddr->AcquireByte	920	Covered	T52,T54,T55
StretchAddr->AcquireStart	997	Covered	T50,T51
StretchAddr->Idle	995	Covered	T50,T51
StretchAddr->StretchTx	920	Not Covered
StretchAddr->WaitForStop	913	Covered	T53
StretchAddrAck->AcquireStart	997	Not Covered
StretchAddrAck->Idle	995	Not Covered
StretchAddrAck->StretchAddrAckSetup	895	Not Covered
StretchAddrAck->WaitForStop	893	Covered	T47,T48,T49
StretchAddrAckSetup->AcquireStart	997	Not Covered
StretchAddrAckSetup->AddrAckSetup	904	Not Covered
StretchAddrAckSetup->Idle	995	Not Covered
StretchAddrAckSetup->WaitForStop	1001	Not Covered
StretchTx->AcquireStart	997	Covered	T50,T51
StretchTx->Idle	995	Covered	T50,T51
StretchTx->StretchTxSetup	936	Covered	T7,T8,T9
StretchTx->WaitForStop	928	Covered	T58,T59,T60
StretchTxSetup->AcquireStart	997	Covered	T50,T51
StretchTxSetup->Idle	995	Covered	T50,T51
StretchTxSetup->TransmitSetup	947	Covered	T7,T8,T9
StretchTxSetup->WaitForStop	1001	Not Covered
TransmitAck->AcquireStart	997	Covered	T50,T51
TransmitAck->Idle	995	Covered	T50,T51
TransmitAck->TransmitAckPulse	821	Covered	T7,T8,T9
TransmitAck->WaitForStop	1001	Not Covered
TransmitAckPulse->AcquireStart	997	Covered	T50,T51
TransmitAckPulse->Idle	995	Covered	T50,T51
TransmitAckPulse->TransmitWait	830	Covered	T7,T8,T9
TransmitAckPulse->WaitForStop	833	Covered	T7,T8,T9
TransmitHold->AcquireStart	997	Covered	T50,T51
TransmitHold->Idle	995	Covered	T50,T51
TransmitHold->TransmitAck	810	Covered	T7,T8,T9
TransmitHold->TransmitSetup	814	Covered	T7,T8,T9
TransmitHold->WaitForStop	1001	Not Covered
TransmitPulse->AcquireStart	997	Covered	T50,T51
TransmitPulse->Idle	995	Covered	T50,T51
TransmitPulse->TransmitHold	801	Covered	T7,T8,T9
TransmitPulse->WaitForStop	1001	Not Covered
TransmitSetup->AcquireStart	997	Covered	T50,T51
TransmitSetup->Idle	995	Covered	T50,T51
TransmitSetup->TransmitPulse	796	Covered	T7,T8,T9
TransmitSetup->WaitForStop	1001	Not Covered
TransmitWait->AcquireStart	997	Covered	T50,T51
TransmitWait->Idle	995	Covered	T50,T51
TransmitWait->StretchTx	789	Covered	T7,T8,T9
TransmitWait->TransmitSetup	791	Covered	T7,T8,T9
TransmitWait->WaitForStop	1001	Not Covered
WaitForStop->AcquireStart	997	Covered	T7,T8,T9
WaitForStop->Idle	995	Covered	T7,T8,T9

---

Branch Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
Branches		165	138	83.64
IF	131	6	4	66.67
IF	144	2	2	100.00
IF	154	4	4	100.00
IF	165	3	3	100.00
IF	182	2	2	100.00
IF	191	2	2	100.00
IF	200	2	2	100.00
IF	216	5	5	100.00
IF	239	5	5	100.00
IF	250	4	4	100.00
IF	302	3	3	100.00
CASE	352	44	37	84.09
IF	623	5	4	80.00
CASE	680	69	54	78.26
IF	986	5	3	60.00
IF	1007	2	2	100.00
IF	1016	2	2	100.00

131            if (load_tcount) begin
               -1-  
132              unique case (tcount_sel)
                        -2-  
133                tSetupData  : tcount_d = 13'(t_r_i) + 13'(tsu_dat_i);
                   ==>
134                tHoldData   : tcount_d = 16'(thd_dat_i);
                   ==>
135                tNoDelay    : tcount_d = 16'h0001;
                   ==>
136                default     : tcount_d = 16'h0001;
                   ==>
137              endcase
138            end else if (target_enable_i) begin
                        -3-  
139              tcount_d = tcount_q - 1'b1;
                 ==>
140            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupData	-	Covered	T6,T7,T8
1	tHoldData	-	Covered	T6,T7,T8
1	tNoDelay	-	Not Covered
1	default	-	Not Covered
0	-	1	Covered	T6,T7,T8
0	-	0	Covered	T1,T2,T3

144            if (!rst_ni) begin
               -1-  
145              tcount_q <= '1;
                 ==>
146            end else begin
147              tcount_q <= tcount_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

154            if (!rst_ni) begin
               -1-  
155              stretch_active_cnt <= '0;
                 ==>
156            end else if (actively_stretching) begin
                        -2-  
157              stretch_active_cnt <= stretch_active_cnt + 1'b1;
                 ==>
158            end else if (start_detect_i && target_idle_o) begin
                        -3-  
159              stretch_active_cnt <= '0;
                 ==>
160            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

165            if (!rst_ni) begin
               -1-  
166              auto_ack_cnt_q <= '0;
                 ==>
167            end else if (auto_ack_load_i && ack_ctrl_stretching) begin
                        -2-  
168              // Loads are only accepted while stretching to avoid races.
169              auto_ack_cnt_q <= auto_ack_load_value_i;
                 ==>
170            end else begin
171              auto_ack_cnt_q <= auto_ack_cnt_d;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

182            if (!rst_ni) begin
               -1-  
183              nack_transaction_q <= 1'b0;
                 ==>
184            end else begin
185              nack_transaction_q <= nack_transaction_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191            if (!rst_ni) begin
               -1-  
192              scl_i_q <= 1'b1;
                 ==>
193            end else begin
194              scl_i_q <= scl_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

200            if (!rst_ni) begin
               -1-  
201              restart_det_q <= 1'b0;
                 ==>
202              xact_for_us_q <= 1'b0;
203              xfer_for_us_q <= 1'b0;
204            end else begin
205              restart_det_q <= restart_det_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

216            if (!rst_ni) begin
               -1-  
217              bit_idx <= 4'd0;
                 ==>
218            end else if (start_detect_i) begin
                        -2-  
219              bit_idx <= 4'd0;
                 ==>
220            end else if (scl_i_q && !scl_i) begin
                        -3-  
221              // input byte clear is always asserted on a "start"
222              // condition.
223              if (input_byte_clr || bit_ack) bit_idx <= 4'd0;
                 -4-  
                 ==>
224              else bit_idx <= bit_idx + 1'b1;
                 ==>
225            end else begin
226              bit_idx <= bit_idx;
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T3,T5
0	0	1	1	Covered	T3,T4,T5
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

239            if (!rst_ni) begin
               -1-  
240              input_byte <= 8'h00;
                 ==>
241            end else if (input_byte_clr) begin
                        -2-  
242              input_byte <= 8'h00;
                 ==>
243            end else if (!scl_i_q && scl_i) begin
                        -3-  
244              if (!bit_ack) input_byte[7:0] <= {input_byte[6:0], sda_i};  // MSB goes in first
                 -4-  
                 ==>
                 MISSING_ELSE
                 ==>
245            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T7,T8
0	0	1	1	Covered	T1,T3,T4
0	0	1	0	Covered	T3,T4,T5
0	0	0	-	Covered	T1,T2,T3

250            if (!rst_ni) begin
               -1-  
251              host_ack <= 1'b0;
                 ==>
252            end else if (!scl_i_q && scl_i) begin
                        -2-  
253              if (bit_ack) host_ack <= ~sda_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>
254            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T3,T4,T5
0	1	0	Covered	T1,T3,T4
0	0	-	Covered	T1,T2,T3

302            if (!rst_ni) begin
               -1-  
303              rw_bit_q <= '0;
                 ==>
304            end else if (bit_ack && address_match) begin
                        -2-  
305              rw_bit_q <= rw_bit;
                 ==>
306            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

352            unique case (state_q)
                      -1-  
353              // Idle: initial state, SDA is released (high), SCL is released if the
354              // bus is idle. Otherwise, if no STOP condition has been sent yet,
355              // continue pulling SCL low in host mode.
356              Idle : begin
357                sda_d = 1'b1;
                   ==>
358                scl_d = 1'b1;
359                restart_det_d = 1'b0;
360                xact_for_us_d = 1'b0;
361                xfer_for_us_d = 1'b0;
362                nack_transaction_d = 1'b0;
363              end
364        
365              /////////////////
366              // TARGET MODE //
367              /////////////////
368        
369              // AcquireStart: hold for the end of the start condition
370              AcquireStart : begin
371                target_idle_o = 1'b0;
                   ==>
372                xfer_for_us_d = 1'b0;
373                auto_ack_cnt_d = '0;
374              end
375              // AddrRead: read and compare target address
376              AddrRead : begin
377                target_idle_o = 1'b0;
378                rw_bit = input_byte[0];
379        
380                if (bit_ack) begin
                   -2-  
381                  if (address_match) begin
                     -3-  
382                    xact_for_us_d = 1'b1;
                       ==>
383                    xfer_for_us_d = 1'b1;
384                  end
                     MISSING_ELSE
                     ==>
385                end
                   MISSING_ELSE
                   ==>
386              end
387              // AddrAckWait: pause for hold time before acknowledging
388              AddrAckWait : begin
389                target_idle_o = 1'b0;
390        
391                if (scl_i) begin
                   -4-  
392                  // The controller is going too fast. Abandon the transaction.
393                  // Nothing gets recorded for this case.
394                  nack_transaction_d = 1'b1;
                     ==>
395                end
                   MISSING_ELSE
                   ==>
396              end
397              // AddrAckSetup: target pulls SDA low while SCL is low
398              AddrAckSetup : begin
399                target_idle_o = 1'b0;
                   ==>
400                sda_d = 1'b0;
401                transmitting_o = 1'b1;
402              end
403              // AddrAckPulse: target pulls SDA low while SCL is released
404              AddrAckPulse : begin
405                target_idle_o = 1'b0;
                   ==>
406                sda_d = 1'b0;
407                transmitting_o = 1'b1;
408              end
409              // AddrAckHold: target pulls SDA low while SCL is pulled low
410              AddrAckHold : begin
411                target_idle_o = 1'b0;
412                sda_d = 1'b0;
413                transmitting_o = 1'b1;
414        
415                // Upon transition to next state, populate the acquisition fifo
416                if (tcount_q == 20'd1) begin
                   -5-  
417                  if (nack_transaction_q) begin
                     -6-  
                     ==>
418                    // No need to record anything here. We already recorded the first
419                    // NACK'd byte in a stretch state or abandoned the transaction in
420                    // AddrAckWait.
421                  end else if (!stretch_addr) begin
                              -7-  
422                    // Only write to fifo if stretching conditions are not met
423                    acq_fifo_wvalid_o = 1'b1;
                       ==>
424                    event_read_cmd_received_o = rw_bit_q;
425                  end
                     MISSING_ELSE
                     ==>
426        
427                  if (restart_det_q) begin
                     -8-  
428                    acq_fifo_wdata_o = {AcqRestart, input_byte};
                       ==>
429                  end else begin
430                    acq_fifo_wdata_o = {AcqStart, input_byte};
                       ==>
431                  end
432                end
                   MISSING_ELSE
                   ==>
433              end
434              // TransmitWait: Check if data is available prior to transmit
435              TransmitWait : begin
436                target_idle_o = 1'b0;
                   ==>
437              end
438              // TransmitSetup: target shifts indexed bit onto SDA while SCL is low
439              TransmitSetup : begin
440                target_idle_o = 1'b0;
                   ==>
441                sda_d = tx_fifo_rdata[3'(bit_idx)];
442                transmitting_o = 1'b1;
443              end
444              // TransmitPulse: target holds indexed bit onto SDA while SCL is released
445              TransmitPulse : begin
446                target_idle_o = 1'b0;
                   ==>
447        
448                // Hold value
449                sda_d = sda_q;
450                transmitting_o = 1'b1;
451              end
452              // TransmitHold: target holds indexed bit onto SDA while SCL is pulled low, for the hold time
453              TransmitHold : begin
454                target_idle_o = 1'b0;
                   ==>
455        
456                // Hold value
457                sda_d = sda_q;
458                transmitting_o = 1'b1;
459              end
460              // TransmitAck: target waits for host to ACK transmission
461              TransmitAck : begin
462                target_idle_o = 1'b0;
                   ==>
463              end
464              TransmitAckPulse : begin
465                target_idle_o = 1'b0;
466                if (!scl_i) begin
                   -9-  
467                  // Pop Fifo regardless of ack/nack
468                  tx_fifo_rready_o = 1'b1;
                     ==>
469                end
                   MISSING_ELSE
                   ==>
470              end
471              // WaitForStop just waiting for host to trigger a stop after nack
472              WaitForStop : begin
473                target_idle_o = 1'b0;
                   ==>
474                expect_stop = 1'b1;
475                sda_d = 1'b1;
476              end
477              // AcquireByte: target acquires a byte
478              AcquireByte : begin
479                target_idle_o = 1'b0;
                   ==>
480              end
481              // AcquireAckWait: pause before acknowledging
482              AcquireAckWait : begin
483                target_idle_o = 1'b0;
484                if (scl_i) begin
                   -10-  
485                  // The controller is going too fast. Abandon the transaction.
486                  // Nothing is recorded for this case.
487                  nack_transaction_d = 1'b1;
                     ==>
488                end
                   MISSING_ELSE
                   ==>
489              end
490              // AcquireAckSetup: target pulls SDA low while SCL is low
491              AcquireAckSetup : begin
492                target_idle_o = 1'b0;
                   ==>
493                sda_d = 1'b0;
494                transmitting_o = 1'b1;
495              end
496              // AcquireAckPulse: target pulls SDA low while SCL is released
497              AcquireAckPulse : begin
498                target_idle_o = 1'b0;
                   ==>
499                sda_d = 1'b0;
500                transmitting_o = 1'b1;
501              end
502              // AcquireAckHold: target pulls SDA low while SCL is pulled low
503              AcquireAckHold : begin
504                target_idle_o = 1'b0;
505                sda_d = 1'b0;
506                transmitting_o = 1'b1;
507        
508                if (tcount_q == 20'd1) begin
                   -11-  
509                  auto_ack_cnt_d = auto_ack_cnt_q - 1'b1;
                     ==>
510                  acq_fifo_wvalid_o = ~stretch_rx;          // assert that acq_fifo has space
511                  acq_fifo_wdata_o = {AcqData, input_byte}; // transfer data to acq_fifo
512                end
                   MISSING_ELSE
                   ==>
513              end
514              // StretchAddrAck: target stretches the clock if matching address cannot be
515              // deposited yet. (During ACK phase)
516              StretchAddrAck : begin
517                target_idle_o = 1'b0;
518                scl_d = 1'b0;
519                actively_stretching = stretch_addr;
520        
521                if (nack_timeout) begin
                   -12-  
522                  nack_transaction_d = 1'b1;
                     ==>
523                  // Record NACK'd Start bytes as long as there is space.
524                  // The next state is always WaitForStop, so the ACQ FIFO needs to be
525                  // written here.
526                  acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
527                  acq_fifo_wdata_o = {AcqNackStart, input_byte};
528                end
                   MISSING_ELSE
                   ==>
529              end
530              // StretchAddrAckSetup: target pulls SDA low while pulling SCL low for
531              // setup time. This is to prepare the setup time after a stretch.
532              StretchAddrAckSetup : begin
533                target_idle_o = 1'b0;
                   ==>
534                sda_d = 1'b0;
535                scl_d = 1'b0;
536                transmitting_o = 1'b1;
537              end
538              // StretchAddr: target stretches the clock if matching address cannot be
539              // deposited yet.
540              StretchAddr : begin
541                target_idle_o = 1'b0;
542                scl_d = 1'b0;
543                actively_stretching = stretch_addr;
544        
545                if (nack_timeout) begin
                   -13-  
546                  nack_transaction_d = 1'b1;
                     ==>
547                  // Record NACK'd Start bytes as long as there is space.
548                  // The next state is always WaitForStop, so the ACQ FIFO needs to be
549                  // written here.
550                  acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
551                  acq_fifo_wdata_o = {AcqNackStart, input_byte};
552                end else if (!stretch_addr) begin
                            -14-  
553                  acq_fifo_wvalid_o = 1'b1;
554                  if (restart_det_q) begin
                     -15-  
555                    acq_fifo_wdata_o = {AcqRestart, input_byte};
                       ==>
556                  end else begin
557                    acq_fifo_wdata_o = {AcqStart, input_byte};
                       ==>
558                  end
559                end
                   MISSING_ELSE
                   ==>
560              end
561              // StretchTx: target stretches the clock when tx_fifo is empty
562              StretchTx : begin
563                target_idle_o = 1'b0;
564                scl_d = 1'b0;
565                actively_stretching = stretch_tx;
566        
567                if (nack_timeout) begin
                   -16-  
568                  // Only the NackStop will get recorded (later) to provide ACQ FIFO
569                  // history of the failed transaction. Meanwhile, the NACK timeout
570                  // will still get reported.
571                  nack_transaction_d = 1'b1;
                     ==>
572                end
                   MISSING_ELSE
                   ==>
573              end
574              // StretchTxSetup: drive the return data
575              StretchTxSetup : begin
576                target_idle_o = 1'b0;
                   ==>
577                scl_d = 1'b0;
578                sda_d = tx_fifo_rdata[3'(bit_idx)];
579                transmitting_o = 1'b1;
580              end
581              // StretchAcqFull: target stretches the clock when acq_fifo is full
582              StretchAcqFull : begin
583                target_idle_o = 1'b0;
584                scl_d = 1'b0;
585                ack_ctrl_stretching = !can_auto_ack;
586                actively_stretching = stretch_rx;
587        
588        
589                if (nack_timeout || (sw_nack_i && !can_auto_ack)) begin
                   -17-  
590                  nack_transaction_d = 1'b1;
                     ==>
591                  acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
592                  acq_fifo_wdata_o = {AcqNack, input_byte};
593                end
                   MISSING_ELSE
                   ==>
594              end
595              // StretchAcqSetup: Drive the ACK and wait for tSetupData before
596              // releasing SCL
597              StretchAcqSetup : begin
598                target_idle_o = 1'b0;
                   ==>
599                scl_d = 1'b0;
600                sda_d = 1'b0;
601                transmitting_o = 1'b1;
602              end
603              // default
604              default : begin
605                target_idle_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T64,T65
AddrRead	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckWait	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T50,T51,T52
AddrAckHold	-	-	-	1	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
AddrAckHold	-	-	-	1	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAckPulse	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAckPulse	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T47,T48,T49
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T47,T48,T49
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T53
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	Covered	T52,T54,T55
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	Covered	T54,T56,T57
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T50,T51,T52
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T58,T59,T60
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T7,T8,T9
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T61,T62,T63
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

623            if (target_enable_i && (stop_detect_i || bus_timeout_i)) begin
               -1-  
624              event_cmd_complete_o = xfer_for_us_q;
625              event_tx_bus_timeout_o = bus_timeout_i && rw_bit_q;
626              // Note that we assume the ACQ FIFO can accept a new item and will
627              // receive the arbiter grant without delay. No other FIFOs should have
628              // activity during a Start or Stop symbol.
629              // TODO: Add an assertion.
630              acq_fifo_wvalid_o = xact_for_us_q;
631              if (nack_transaction_q || bus_timeout_i) begin
                 -2-  
632                acq_fifo_wdata_o = {AcqNackStop, input_byte};
                   ==>
633              end else begin
634                acq_fifo_wdata_o = {AcqStop, input_byte};
                   ==>
635              end
636            end else if (target_enable_i && start_detect_i) begin
                        -3-  
637              restart_det_d = !target_idle_o;
                 ==>
638              event_cmd_complete_o = xfer_for_us_q;
639            end else if (arbitration_lost_i) begin
                        -4-  
640              nack_transaction_d = 1'b1;
                 ==>
641              event_cmd_complete_o = xfer_for_us_q;
642              event_tx_arbitration_lost_o = rw_bit_q;
643            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T61,T62,T58
1	0	-	-	Covered	T6,T7,T8
0	-	1	-	Covered	T6,T7,T8
0	-	0	1	Not Covered
0	-	0	0	Covered	T1,T2,T3

680            unique case (state_q)
                      -1-  
681              // Idle: initial state, SDA and SCL are released (high)
682              Idle : begin
                 ==>
683                // The bus is idle. Waiting for a Start.
684              end
685        
686              /////////////////
687              // TARGET MODE //
688              /////////////////
689        
690              // AcquireStart: hold for the end of the start condition
691              AcquireStart : begin
692                if (!scl_i) begin
                   -2-  
693                  state_d = AddrRead;
                     ==>
694                  input_byte_clr = 1'b1;
695                end
                   MISSING_ELSE
                   ==>
696              end
697              // AddrRead: read and compare target address
698              AddrRead : begin
699                // bit_ack goes high the cycle after scl_i goes low, after the 8th bit
700                // was captured.
701                if (bit_ack) begin
                   -3-  
702                  if (address_match) begin
                     -4-  
703                    state_d = AddrAckWait;
                       ==>
704                    // Wait for hold time to avoid interfering with the controller.
705                    load_tcount = 1'b1;
706                    tcount_sel = tHoldData;
707                  end else begin // !address_match
708                    // This means this transfer is not meant for us.
709                    state_d = WaitForStop;
                       ==>
710                  end
711                end
                   MISSING_ELSE
                   ==>
712              end
713              // AddrAckWait: pause for hold time before acknowledging
714              AddrAckWait : begin
715                if (scl_i) begin
                   -5-  
716                  // The controller is going too fast. Abandon the transaction.
717                  state_d = WaitForStop;
                     ==>
718                end else if (tcount_q == 20'd1) begin
                            -6-  
719                  if (!nack_addr_after_timeout_i) begin
                     -7-  
720                    // Always ACK addresses in this mode.
721                    state_d = AddrAckSetup;
                       ==>
722                  end else begin
723                    if (nack_transaction_q) begin
                       -8-  
724                      // We must have stretched before, and software has been notified
725                      // through an ACQ FIFO full event. For writes we should NACK all
726                      // bytes in the transfer unconditionally. For reads, we NACK
727                      // the address byte, then release SDA for the rest of the
728                      // transfer.
729                      // Essentially, we're waiting for the end of the transaction.
730                      state_d = WaitForStop;
                         ==>
731                    end else if (stretch_addr) begin
                                -9-  
732                      // Not enough bytes to capture the Start/address byte, but might
733                      // need to NACK.
734                      state_d = StretchAddrAck;
                         ==>
735                    end else begin
736                      // The transaction hasn't already been NACK'd, and there is
737                      // room in the ACQ FIFO. Proceed.
738                      state_d = AddrAckSetup;
                         ==>
739                    end
740                  end
741                end
                   MISSING_ELSE
                   ==>
742              end
743              // AddrAckSetup: target pulls SDA low while SCL is low
744              AddrAckSetup : begin
745                if (scl_i) state_d = AddrAckPulse;
                   -10-  
                   ==>
                   MISSING_ELSE
                   ==>
746              end
747              // AddrAckPulse: target pulls SDA low while SCL is released
748              AddrAckPulse : begin
749                if (!scl_i) begin
                   -11-  
750                  state_d = AddrAckHold;
                     ==>
751                  load_tcount = 1'b1;
752                  tcount_sel = tHoldData;
753                end
                   MISSING_ELSE
                   ==>
754              end
755              // AddrAckHold: target pulls SDA low while SCL is pulled low
756              AddrAckHold : begin
757                if (tcount_q == 20'd1) begin
                   -12-  
758                  // Stretch when requested by software or when there is insufficient
759                  // space to hold the start / address format byte.
760                  // If there is sufficient space, the format byte is written into the acquisition fifo.
761                  // Don't stretch when we are unconditionally nacking the next byte
762                  // anyways.
763                  if (nack_transaction_q) begin
                     -13-  
764                    // If the Target is set to NACK already, release SDA and wait
765                    // for a Stop. This isn't an ideal response for SMBus reads, since
766                    // 127 bytes of 0xff will just happen to have a correct PEC. It's
767                    // best for software to ensure there is always space in the ACQ
768                    // FIFO.
769                    state_d = WaitForStop;
                       ==>
770                  end else if (stretch_addr) begin // !nack_transaction_q
                              -14-  
771                    // Stretching because there is insufficient space to hold the
772                    // start / address format byte.
773                    // We should only reach here with !nack_addr_after_timeout_i, since
774                    // we had enough space for nack_addr_after_timeout_i already,
775                    // before issuing the ACK.
776                    state_d = StretchAddr;
                       ==>
777                  end else if (rw_bit_q) begin
                              -15-  
778                    // Not NACKing automatically, not stretching, and it's a read.
779                    state_d = TransmitWait;
                       ==>
780                  end else begin
781                    // Not NACKing automatically, not stretching, and it's a write.
782                    state_d = AcquireByte;
                       ==>
783                  end
784                end
                   MISSING_ELSE
                   ==>
785              end
786              // TransmitWait: Evaluate whether there are entries to send first
787              TransmitWait : begin
788                if (stretch_tx) begin
                   -16-  
789                  state_d = StretchTx;
                     ==>
790                end else begin
791                  state_d = TransmitSetup;
                     ==>
792                end
793              end
794              // TransmitSetup: target shifts indexed bit onto SDA while SCL is low
795              TransmitSetup : begin
796                if (scl_i) state_d = TransmitPulse;
                   -17-  
                   ==>
                   MISSING_ELSE
                   ==>
797              end
798              // TransmitPulse: target shifts indexed bit onto SDA while SCL is released
799              TransmitPulse : begin
800                if (!scl_i) begin
                   -18-  
801                  state_d = TransmitHold;
                     ==>
802                  load_tcount = 1'b1;
803                  tcount_sel = tHoldData;
804                end
                   MISSING_ELSE
                   ==>
805              end
806              // TransmitHold: target shifts indexed bit onto SDA while SCL is pulled low
807              TransmitHold : begin
808                if (tcount_q == 20'd1) begin
                   -19-  
809                  if (bit_ack) begin
                     -20-  
810                    state_d = TransmitAck;
                       ==>
811                  end else begin
812                    load_tcount = 1'b1;
                       ==>
813                    tcount_sel = tHoldData;
814                    state_d = TransmitSetup;
815                  end
816                end
                   MISSING_ELSE
                   ==>
817              end
818              // Wait for clock to become positive.
819              TransmitAck : begin
820                if (scl_i) begin
                   -21-  
821                  state_d = TransmitAckPulse;
                     ==>
822                end
                   MISSING_ELSE
                   ==>
823              end
824              // TransmitAckPulse: target waits for host to ACK transmission
825              // If a nak is received, that means a stop is incoming.
826              TransmitAckPulse : begin
827                if (!scl_i) begin
                   -22-  
828                  // If host acknowledged, that means we must continue
829                  if (host_ack) begin
                     -23-  
830                    state_d = TransmitWait;
                       ==>
831                  end else begin
832                    // If host nak'd then the transaction is about to terminate, go to a wait state
833                    state_d = WaitForStop;
                       ==>
834                  end
835                end
                   MISSING_ELSE
                   ==>
836              end
837              // An inert state just waiting for host to issue a stop
838              // Cannot cycle back to idle directly as other events depend on the system being
839              // non-idle.
840              WaitForStop : begin
841                state_d = WaitForStop;
                   ==>
842              end
843              // AcquireByte: target acquires a byte
844              AcquireByte : begin
845                if (bit_ack) begin
                   -24-  
846                  state_d = AcquireAckWait;
                     ==>
847                  load_tcount = 1'b1;
848                  tcount_sel = tHoldData;
849                end
                   MISSING_ELSE
                   ==>
850              end
851              // AcquireAckWait: pause for hold time before acknowledging
852              AcquireAckWait : begin
853                if (scl_i) begin
                   -25-  
854                  // The controller is going too fast. Abandon the transaction.
855                  state_d = WaitForStop;
                     ==>
856                end else if (tcount_q == 20'd1) begin
                            -26-  
857                  if (nack_transaction_q) begin
                     -27-  
858                    state_d = WaitForStop;
                       ==>
859                  end else if (stretch_rx) begin
                              -28-  
860                    // If there is no space for the current entry, stretch clocks and
861                    // wait for software to make space. Also stretch if ACK Control
862                    // Mode is enabled and the auto_ack_cnt is exhausted.
863                    state_d = StretchAcqFull;
                       ==>
864                  end else begin
865                    state_d = AcquireAckSetup;
                       ==>
866                  end
867                end
                   MISSING_ELSE
                   ==>
868              end
869              // AcquireAckSetup: target pulls SDA low while SCL is low
870              AcquireAckSetup : begin
871                if (scl_i) state_d = AcquireAckPulse;
                   -29-  
                   ==>
                   MISSING_ELSE
                   ==>
872              end
873              // AcquireAckPulse: target pulls SDA low while SCL is released
874              AcquireAckPulse : begin
875                if (!scl_i) begin
                   -30-  
876                  state_d = AcquireAckHold;
                     ==>
877                  load_tcount = 1'b1;
878                  tcount_sel = tHoldData;
879                end
                   MISSING_ELSE
                   ==>
880              end
881              // AcquireAckHold: target pulls SDA low while SCL is pulled low
882              AcquireAckHold : begin
883                if (tcount_q == 20'd1) begin
                   -31-  
884                  state_d = AcquireByte;
                     ==>
885                end
                   MISSING_ELSE
                   ==>
886              end
887              // StretchAddrAck: The address phase can not yet be completed, stretch
888              // clock and wait.
889              StretchAddrAck : begin
890                // When there is space in the FIFO go to the next state.
891                // If we hit our nack timeout, we must nack the full transaction.
892                if (nack_timeout) begin
                   -32-  
893                  state_d = WaitForStop;
                     ==>
894                end else if (!stretch_addr) begin
                            -33-  
895                  state_d = StretchAddrAckSetup;
                     ==>
896                  load_tcount = 1'b1;
897                  tcount_sel = tSetupData;
898                end
                   MISSING_ELSE
                   ==>
899              end
900              // StretchAddrAckSetup: target pulls SDA low while pulling SCL low for
901              // setup time. This is to prepare the setup time after a stretch.
902              StretchAddrAckSetup : begin
903                if (tcount_q == 20'd1) begin
                   -34-  
904                  state_d = AddrAckSetup;
                     ==>
905                end
                   MISSING_ELSE
                   ==>
906              end
907              // StretchAddr: The address phase can not yet be completed, stretch
908              // clock and wait.
909              StretchAddr : begin
910                // When there is space in the FIFO go to the next state.
911                // If we hit our nack timeout, we must nack the full transaction.
912                if (nack_timeout) begin
                   -35-  
913                  state_d = WaitForStop;
                     ==>
914                end else if (!stretch_addr) begin
                            -36-  
915                  // When transmitting after an address stretch, we need to assume
916                  // that it looks like a Tx stretch.  This is because if we try
917                  // to follow the normal path, the logic will release the clock
918                  // too early relative to driving the data.  This will cause a
919                  // setup violation.  This is the same case to needing StretchTxSetup.
920                  state_d = rw_bit_q ? StretchTx : AcquireByte;
                                        -37-  
                                        ==>  
                                        ==>  
921                end
                   MISSING_ELSE
                   ==>
922              end
923              // StretchTx: target stretches the clock when tx conditions are not satisfied.
924              StretchTx : begin
925                // When in stretch state, always notify software that help is required.
926                event_tx_stretch_o = 1'b1;
927                if (nack_timeout) begin
                   -38-  
928                  state_d = WaitForStop;
                     ==>
929                end else if (!stretch_tx) begin
                            -39-  
930                  // When data becomes available, we must first drive it onto the line
931                  // for at least the "setup" period.  If we do not, once the clock is released, the
932                  // pull-up in the system will likely immediately trigger a rising clock
933                  // edge (since the stretch likely pushed us way beyond the original intended
934                  // rise).  If we do not artificially create the setup period here, it will
935                  // likely create a timing violation.
936                  state_d = StretchTxSetup;
                     ==>
937                  load_tcount = 1'b1;
938                  tcount_sel = tSetupData;
939        
940                  // When leaving stretch state, de-assert software notification
941                  event_tx_stretch_o = 1'b0;
942                end
                   MISSING_ELSE
                   ==>
943              end
944              // StretchTxSetup: Wait for tSetupData before going to transmit
945              StretchTxSetup : begin
946                if (tcount_q == 20'd1) begin
                   -40-  
947                  state_d = TransmitSetup;
                     ==>
948                end
                   MISSING_ELSE
                   ==>
949              end
950              // StretchAcqFull: target stretches the clock when acq_fifo is full
951              // When space becomes available, move on to prepare to ACK. If we hit
952              // our NACK timeout we must continue and unconditionally NACK the next
953              // one.
954              // If ACK Control Mode is enabled, also stretch if the Auto ACK counter
955              // is exhausted. If the conditions for an ACK Control stretch are
956              // present, NACK the transaction if directed by SW.
957              StretchAcqFull : begin
958                if (nack_timeout || (sw_nack_i && !can_auto_ack)) begin
                   -41-  
959                  state_d = WaitForStop;
                     ==>
960                end else if (~stretch_rx) begin
                            -42-  
961                  state_d = StretchAcqSetup;
                     ==>
962                  load_tcount = 1'b1;
963                  tcount_sel = tSetupData;
964                end
                   MISSING_ELSE
                   ==>
965              end
966              // StretchAcqSetup: Drive the ACK and wait for tSetupData before
967              // releasing SCL
968              StretchAcqSetup : begin
969                if (tcount_q == 20'd1) begin
                   -43-  
970                  state_d = AcquireAckSetup;
                     ==>
971                end
                   MISSING_ELSE
                   ==>
972              end
973              // default
974              default : begin
975                state_d = Idle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireStart	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T64,T65
AddrRead	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckWait	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T47,T48,T49
AddrAckWait	-	-	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T62,T47,T66
AddrAckWait	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckSetup	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T50,T51,T52
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T47,T48,T49
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T47,T48,T49
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T53
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	-	-	Covered	T52,T54,T55
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T50,T51,T52
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T58,T59,T60
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T7,T8,T9
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T7,T8,T9
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T8,T9
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T7,T8,T9
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T61,T62,T63
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T7,T10
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T7,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

986            if (!target_idle && !target_enable_i) begin
               -1-  
987              // If the target function is currently not idle but target_enable is suddenly dropped,
988              // (maybe because the host locked up and we want to cycle back to an initial state),
989              // transition immediately.
990              // The same treatment is not given to the host mode because it already attempts to
991              // gracefully terminate.  If the host cannot gracefully terminate for whatever reason,
992              // (the other side is holding SCL low), we may need to forcefully reset the module.
993              // ICEBOX(#18004): It may be worth having a force stop condition to force the host back to
994              // Idle in case graceful termination is not possible.
995              state_d = Idle;
                 ==>
996            end else if (target_enable_i && start_detect_i) begin
                        -2-  
997              state_d = AcquireStart;
                 ==>
998            end else if (stop_detect_i || bus_timeout_i) begin
                        -3-  
999              state_d = Idle;
                 ==>
1000           end else if (arbitration_lost_i) begin
                        -4-  
1001             state_d = WaitForStop;
                 ==>
1002           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Covered	T6,T7,T8
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

1007           if (!rst_ni) begin
               -1-  
1008             state_q <= Idle;
                 ==>
1009           end else begin
1010             state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1016           if (!rst_ni) begin
               -1-  
1017             sda_q <= 1'b1;
                 ==>
1018           end else begin
1019             sda_q <= sda_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_target_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	390033414	993693	0	0
AcqFifoDeepEnough_A	390033414	389859396	0	0
SclOutputGlitch_A	390033414	60921	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	993693	0	0
T7	20083	256	0	0
T8	26088	357	0	0
T9	12628	4882	0	0
T10	78164	0	0	0
T45	48225	0	0	0
T46	133362	1507	0	0
T50	0	665	0	0
T69	136411	1471	0	0
T70	0	271	0	0
T71	0	1571	0	0
T72	0	1605	0	0
T73	0	486	0	0
T74	995	0	0	0
T75	3897	0	0	0
T76	44336	0	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	389859396	0	0
T1	1646	1586	0	0
T2	9765	9689	0	0
T3	14401	14339	0	0
T4	5432	5352	0	0
T5	14001	13227	0	0
T6	7532	7451	0	0
T7	20083	19996	0	0
T8	26088	26031	0	0
T9	12628	12578	0	0
T10	78164	78072	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	60921	0	0
T6	7532	3	0	0
T7	20083	4	0	0
T8	26088	6	0	0
T9	12628	4	0	0
T10	78164	14	0	0
T45	48225	0	0	0
T46	133362	32	0	0
T61	0	1	0	0
T69	136411	47	0	0
T70	0	1	0	0
T71	0	56	0	0
T74	995	0	0	0
T75	3897	0	0	0