Unified Coverage Report :: Module :: i2c_controller_fsm

Module : i2c_controller_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.63	90.34	75.91		66.67	85.25	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_controller_fsm	83.63	90.34	75.91		66.67	85.25	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_controller_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.63	90.34	75.91		66.67	85.25	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.63	90.34	75.91		66.67	85.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.58	97.74	79.23			93.33	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
TOTAL		435	393	90.34
ALWAYS	121	15	15	100.00
ALWAYS	146	3	3	100.00
ALWAYS	159	5	5	100.00
CONT_ASSIGN	182	1	1	100.00
ALWAYS	186	6	6	100.00
ALWAYS	202	9	8	88.89
CONT_ASSIGN	217	1	1	100.00
ALWAYS	221	7	7	100.00
ALWAYS	234	6	6	100.00
ALWAYS	245	5	5	100.00
ALWAYS	252	7	7	100.00
ALWAYS	265	5	5	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	284	8	8	100.00
ALWAYS	296	8	7	87.50
ALWAYS	308	3	3	100.00
CONT_ASSIGN	341	1	1	100.00
ALWAYS	346	147	139	94.56
ALWAYS	602	191	159	83.25
ALWAYS	961	3	3	100.00
CONT_ASSIGN	968	1	1	100.00
CONT_ASSIGN	969	1	1	100.00
CONT_ASSIGN	972	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : i2c_controller_fsm

	Total	Covered	Percent
Conditions	274	208	75.91
Logical	274	208	75.91
Non-Logical	0	0
Event	0	0

 LINE       136
 EXPRESSION (host_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T24,T25
1	0	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T23,T24,T25

 LINE       161
 EXPRESSION (stretch_en && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       189
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       246
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T15,T16,T17

 LINE       276
 EXPRESSION (event_sda_unstable_o || sda_interference_i || ctrl_symbol_failed)
             ----------1---------    ---------2--------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T5,T14,T26
1	0	0	Covered	T5,T14,T18

 LINE       286
 EXPRESSION (trans_started && (((!host_enable_i)) || event_arbitration_lost_o))
             ------1------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T14,T18

 LINE       286
 SUB-EXPRESSION (((!host_enable_i)) || event_arbitration_lost_o)
                 ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T14,T18
1	0	Covered	T1,T2,T3

 LINE       298
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T12,T18
1	1	Not Covered

 LINE       341
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) && host_nack_handler_timeout_en_i && ((!unhandled_nak_timeout_i)))
             ----------1----------    ------2------    --------3--------    ---------------4--------------    --------------5-------------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T11,T12,T13
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T11,T12,T13
1	1	1	0	1	Not Covered
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T11,T12,T13

 LINE       341
 SUB-EXPRESSION (state_q == Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION (trans_started && ((!scl_i)) && scl_i_q)
             ------1------    -----2----    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T12,T18
1	1	0	Covered	T5,T12,T18
1	1	1	Not Covered

 LINE       393
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       404
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       430
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       431
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T14,T19
1	0	1	Not Covered
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T14,T18,T19

 LINE       431
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T14,T18

 LINE       454
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T11,T12
1	0	1	1	Covered	T5,T22,T29
1	1	0	1	Covered	T5,T22,T29
1	1	1	0	Covered	T11,T12,T13
1	1	1	1	Covered	T11,T12,T13

 LINE       456
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T14,T18

 LINE       457
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T26,T30
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T5,T14,T18

 LINE       457
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       479
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14
1	1	Not Covered

 LINE       480
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Covered	T20,T21

 LINE       480
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T5,T14,T11

 LINE       489
 EXPRESSION ((bit_index == '0) && (tcount_q == 16'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14
1	1	Covered	T3,T5,T14

 LINE       489
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       489
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       503
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       510
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       515
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14
1	1	Not Covered

 LINE       516
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Not Covered

 LINE       516
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T31,T32,T33

 LINE       525
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       544
 EXPRESSION (((!scl_i)) && scl_i_q)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       555
 EXPRESSION (((!sda_i)) && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       570
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T34,T35
1	0	Covered	T5,T12,T18
1	1	Covered	T3,T4,T5

 LINE       619
 EXPRESSION (unhandled_unexp_nak_i || unhandled_nak_timeout_i || halt_controller_i)
             ----------1----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T14,T18
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       632
 EXPRESSION (trans_started && unhandled_nak_cnt_expired)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Not Covered

 LINE       640
 EXPRESSION (trans_started || bus_free_i)
             ------1------    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T2,T3,T4
1	0	Not Covered

 LINE       644
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       658
 EXPRESSION (((!trans_started)) && ((!scl_i)))
             ---------1--------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T18
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       662
 EXPRESSION (trans_started && ((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             ------1------    -----2----    ------3-----    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Covered	T27,T28,T39
1	1	0	1	Not Covered
1	1	1	0	Covered	T5,T12,T18
1	1	1	1	Not Covered

 LINE       668
 EXPRESSION (trans_started && ((!scl_i)) && scl_i_q)
             ------1------    -----2----    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T12,T18
1	1	0	Covered	T5,T12,T18
1	1	1	Not Covered

 LINE       671
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       679
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       679
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       679
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T26,T27,T28
1	1	Not Covered

 LINE       687
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T22
1	Covered	T3,T4,T5

 LINE       695
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T4,T5

 LINE       708
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T22
1	0	1	Not Covered
1	1	0	Covered	T3,T4,T5
1	1	1	Not Covered

 LINE       712
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T14,T19
1	0	1	Not Covered
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T14,T18,T19

 LINE       712
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T14,T18

 LINE       715
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       715
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       715
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       725
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       728
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       740
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       748
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T5,T14,T18
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       752
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T26,T30
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T5,T14,T18

 LINE       752
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T29,T14

 LINE       756
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T14,T18
1	0	Covered	T3,T4,T5

 LINE       756
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       756
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T14,T18

 LINE       765
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       779
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       787
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T12,T40
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Not Covered

 LINE       791
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Covered	T20,T21

 LINE       791
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T5,T14,T11

 LINE       794
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T14
0	1	Not Covered
1	0	Covered	T3,T5,T14

 LINE       794
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       794
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14
1	1	Not Covered

 LINE       803
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       806
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       819
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       827
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T12,T40
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Not Covered

 LINE       831
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T5,T14
1	1	1	Not Covered

 LINE       831
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T31,T32,T33

 LINE       834
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T14
0	1	Not Covered
1	0	Covered	T3,T5,T14

 LINE       834
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       834
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14
1	1	Not Covered

 LINE       842
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       843
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T3,T5,T14

 LINE       863
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       871
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T11,T41
1	0	1	Not Covered
1	1	0	Covered	T3,T4,T5
1	1	1	Not Covered

 LINE       875
 EXPRESSION (((!scl_i)) && scl_i_q)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       878
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       884
 EXPRESSION (((!sda_i)) && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       909
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T34,T35
1	0	Covered	T5,T12,T18
1	1	Covered	T3,T4,T5

 LINE       922
 EXPRESSION (((!host_enable_i)) && trans_started)
             ---------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T23,T24,T25
1	1	Not Covered

 LINE       927
 EXPRESSION (((!host_enable_i)) || (fmt_fifo_depth_i == 7'b1) || unhandled_unexp_nak_i || ((!trans_started)))
             ---------1--------    -------------2------------    ----------3----------    ---------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	1	0	Covered	T11,T12,T13
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       927
 SUB-EXPRESSION (fmt_fifo_depth_i == 7'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       954
 EXPRESSION (trans_started && (sda_interference_i || ctrl_symbol_failed))
             ------1------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T14,T18

 LINE       954
 SUB-EXPRESSION (sda_interference_i || ctrl_symbol_failed)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T14,T18

 LINE       972
 EXPRESSION (stretch_en && timeout_enable_i && (stretch_idle_cnt > 31'(stretch_timeout_i)))
             -----1----    --------2-------    ---------------------3---------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T42,T13
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T5,T29,T14
1	1	1	Covered	T5,T29,T14

---

FSM Coverage for Module : i2c_controller_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	51	34	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Active	641	Covered	T2,T3,T4
ClockLow	688	Covered	T2,T3,T4
ClockLowAck	729	Covered	T3,T4,T5
ClockPulse	701	Covered	T3,T4,T5
ClockPulseAck	741	Covered	T3,T4,T5
ClockStart	680	Covered	T3,T4,T5
ClockStop	635	Covered	T3,T4,T5
HoldBit	718	Covered	T3,T4,T5
HoldDevAck	757	Covered	T3,T4,T5
HoldStart	672	Covered	T3,T4,T5
HoldStop	879	Covered	T3,T4,T5
HostClockLowAck	807	Covered	T3,T5,T14
HostClockPulseAck	820	Covered	T3,T5,T14
HostHoldBitAck	835	Covered	T3,T5,T14
Idle	661	Covered	T1,T2,T3
PopFmtFifo	771	Covered	T3,T4,T5
ReadClockLow	811	Covered	T3,T5,T14
ReadClockPulse	780	Covered	T3,T5,T14
ReadHoldBit	795	Covered	T3,T5,T14
SetupStart	664	Covered	T3,T4,T5
SetupStop	864	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
Active->ClockLow	914	Covered	T2,T4,T5
Active->Idle	955	Not Covered
Active->ReadClockLow	906	Covered	T3,T5,T14
Active->SetupStart	910	Covered	T3,T4,T5
ClockLow->ClockPulse	701	Covered	T3,T4,T5
ClockLow->Idle	955	Not Covered
ClockLow->SetupStart	698	Covered	T5,T12,T18
ClockLowAck->ClockPulseAck	741	Covered	T3,T4,T5
ClockLowAck->Idle	955	Not Covered
ClockPulse->HoldBit	718	Covered	T3,T4,T5
ClockPulse->Idle	714	Covered	T5,T14,T18
ClockPulseAck->HoldDevAck	757	Covered	T3,T4,T5
ClockPulseAck->Idle	754	Covered	T5,T14,T18
ClockStart->ClockLow	688	Covered	T3,T4,T5
ClockStart->Idle	955	Not Covered
ClockStop->Idle	955	Not Covered
ClockStop->SetupStop	864	Covered	T3,T4,T5
HoldBit->ClockLow	732	Covered	T3,T4,T5
HoldBit->ClockLowAck	729	Covered	T3,T4,T5
HoldBit->Idle	955	Not Covered
HoldDevAck->ClockStop	767	Covered	T4,T5,T22
HoldDevAck->Idle	955	Covered	T5,T14,T18
HoldDevAck->PopFmtFifo	771	Covered	T3,T4,T5
HoldStart->ClockStart	680	Covered	T3,T4,T5
HoldStart->Idle	955	Not Covered
HoldStop->Idle	886	Not Covered
HoldStop->PopFmtFifo	896	Covered	T3,T4,T5
HostClockLowAck->HostClockPulseAck	820	Covered	T3,T5,T14
HostClockLowAck->Idle	955	Not Covered
HostClockPulseAck->HostHoldBitAck	835	Covered	T3,T5,T14
HostClockPulseAck->Idle	833	Not Covered
HostHoldBitAck->ClockStop	845	Covered	T3,T5,T14
HostHoldBitAck->Idle	955	Not Covered
HostHoldBitAck->PopFmtFifo	849	Covered	T5,T14,T11
HostHoldBitAck->ReadClockLow	854	Covered	T3,T5,T14
Idle->Active	641	Covered	T2,T3,T4
Idle->ClockStop	635	Not Covered
PopFmtFifo->Active	933	Covered	T3,T4,T5
PopFmtFifo->ClockStop	924	Not Covered
PopFmtFifo->Idle	929	Covered	T3,T4,T5
ReadClockLow->Idle	955	Not Covered
ReadClockLow->ReadClockPulse	780	Covered	T3,T5,T14
ReadClockPulse->Idle	793	Covered	T20,T21
ReadClockPulse->ReadHoldBit	795	Covered	T3,T5,T14
ReadHoldBit->HostClockLowAck	807	Covered	T3,T5,T14
ReadHoldBit->Idle	955	Not Covered
ReadHoldBit->ReadClockLow	811	Covered	T3,T5,T14
SetupStart->HoldStart	672	Covered	T3,T4,T5
SetupStart->Idle	661	Not Covered
SetupStop->HoldStop	879	Covered	T3,T4,T5
SetupStop->Idle	877	Not Covered

---

Branch Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
Branches		183	156	85.25
IF	122	13	12	92.31
IF	146	2	2	100.00
IF	159	3	3	100.00
IF	186	4	4	100.00
IF	202	4	3	75.00
IF	221	4	4	100.00
IF	234	4	4	100.00
IF	245	3	3	100.00
IF	252	4	4	100.00
IF	265	2	2	100.00
IF	284	5	5	100.00
IF	296	5	4	80.00
IF	308	2	2	100.00
CASE	361	53	44	83.02
CASE	614	71	56	78.87
IF	954	2	2	100.00
IF	961	2	2	100.00

122            if (load_tcount) begin
               -1-  
123              unique case (tcount_sel)
                        -2-  
124                tSetupStart : tcount_d = 13'(t_r_i) + 13'(tsu_sta_i);
                   ==>
125                tHoldStart  : tcount_d = 13'(t_f_i) + 13'(thd_sta_i);
                   ==>
126                tClockStart : tcount_d = 16'(thd_dat_i);
                   ==>
127                tClockLow   : tcount_d = 13'(tlow_i) - 13'(thd_dat_i);
                   ==>
128                tClockPulse : tcount_d = 13'(t_r_i) + 13'(thigh_i);
                   ==>
129                tClockHigh  : tcount_d = 16'(thigh_i);
                   ==>
130                tHoldBit    : tcount_d = 13'(t_f_i) + 13'(thd_dat_i);
                   ==>
131                tClockStop  : tcount_d = 13'(t_f_i) + 13'(tlow_i) - 13'(thd_dat_i);
                   ==>
132                tSetupStop  : tcount_d = 13'(t_r_i) + 13'(tsu_sto_i);
                   ==>
133                tNoDelay    : tcount_d = 16'h0001;
                   ==>
134                default     : tcount_d = 16'h0001;
                   ==>
135              endcase
136            end else if (
                        -3-  
137              host_enable_i ||
138              // If we disable Host-Mode mid-txn, keep counting until the end of
139              // byte, at which point we create a STOP condition then return to Idle.
140              (!host_idle_o && !host_enable_i)) begin
141              tcount_d = tcount_q - 1'b1;
                 ==>
142            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T3,T4,T5
1	tHoldStart	-	Covered	T3,T4,T5
1	tClockStart	-	Covered	T3,T4,T5
1	tClockLow	-	Covered	T2,T3,T4
1	tClockPulse	-	Covered	T3,T4,T5
1	tClockHigh	-	Covered	T3,T4,T5
1	tHoldBit	-	Covered	T3,T4,T5
1	tClockStop	-	Covered	T3,T4,T5
1	tSetupStop	-	Covered	T3,T4,T5
1	tNoDelay	-	Covered	T3,T4,T5
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

146            if (!rst_ni) begin
               -1-  
147              tcount_q <= '1;
                 ==>
148            end else begin
149              tcount_q <= tcount_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

159            if (!rst_ni) begin
               -1-  
160              stretch_idle_cnt <= '0;
                 ==>
161            end else if (stretch_en && !scl_i) begin
                        -2-  
162              // HOST-mode count of clock stretching
163              stretch_idle_cnt <= stretch_idle_cnt + 1'b1;
                 ==>
164            end else begin
165              stretch_idle_cnt <= '0;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

186            if (!rst_ni) begin
               -1-  
187              stretch_predict_cnt_expired <= 1'b0;
                 ==>
188            end else begin
189              if (stretch_idle_cnt == stretch_cnt_threshold) begin
                 -2-  
190                stretch_predict_cnt_expired <= 1'b1;
                   ==>
191              end else if (!stretch_en) begin
                          -3-  
192                stretch_predict_cnt_expired <= 1'b0;
                   ==>
193              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T3,T4,T5

202            if (!rst_ni) begin
               -1-  
203              unhandled_nak_cnt <= '0;
                 ==>
204              unhandled_nak_cnt_expired <= 1'b0;
205            end else if (incr_nak_cnt) begin
                        -2-  
206              // Increment the counter while the FSM is halted in Idle.
207              unhandled_nak_cnt <= unhandled_nak_cnt + 1'b1;
208              if (unhandled_nak_cnt > host_nack_handler_timeout_i) begin
                 -3-  
209                unhandled_nak_cnt_expired <= 1'b1;
                   ==>
210              end
                 MISSING_ELSE
                 ==>
211            end else begin
212              unhandled_nak_cnt <= '0;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Not Covered
0	1	0	Covered	T11,T12,T13
0	0	-	Covered	T1,T2,T3

221            if (!rst_ni) begin
               -1-  
222              bit_index <= 3'd7;
                 ==>
223            end else if (bit_clr) begin
                        -2-  
224              bit_index <= 3'd7;
                 ==>
225            end else if (bit_decr) begin
                        -3-  
226              bit_index <= bit_index - 1'b1;
                 ==>
227            end else begin
228              bit_index <= bit_index;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

234            if (!rst_ni) begin
               -1-  
235              read_byte <= 8'h00;
                 ==>
236            end else if (read_byte_clr) begin
                        -2-  
237              read_byte <= 8'h00;
                 ==>
238            end else if (shift_data_en) begin
                        -3-      
239              read_byte[7:0] <= {read_byte[6:0], sda_i};  // MSB goes in first
                 ==>
240            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T14
0	0	1	Covered	T3,T5,T14
0	0	0	Covered	T1,T2,T3

245            if (!fmt_flag_read_bytes_i) byte_num = 9'd0;
               -1-  
               ==>
246            else if (fmt_byte_i == '0) byte_num = 9'd256;
                    -2-  
               ==>
247            else byte_num = 9'(fmt_byte_i);
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
0	0	Covered	T3,T5,T14

252            if (!rst_ni) begin
               -1-  
253              byte_index <= '0;
                 ==>
254            end else if (byte_clr) begin
                        -2-  
255              byte_index <= byte_num;
                 ==>
256            end else if (byte_decr) begin
                        -3-  
257              byte_index <= byte_index - 1'b1;
                 ==>
258            end else begin
259              byte_index <= byte_index;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T14
0	0	1	Covered	T3,T5,T14
0	0	0	Covered	T1,T2,T3

265            if (!rst_ni) begin
               -1-  
266              scl_i_q <= 1'b1;
                 ==>
267              sda_i_q <= 1'b1;
268            end else begin
269              scl_i_q <= scl_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

284            if (!rst_ni) begin
               -1-  
285              trans_started <= '0;
                 ==>
286            end else if (trans_started && (!host_enable_i || event_arbitration_lost_o)) begin
                        -2-  
287              trans_started <= '0;
                 ==>
288            end else if (log_start) begin
                        -3-  
289              trans_started <= 1'b1;
                 ==>
290            end else if (log_stop) begin
                        -4-  
291              trans_started <= 1'b0;
                 ==>
292            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T5,T14,T18
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3

296            if (!rst_ni) begin
               -1-  
297              pend_restart <= '0;
                 ==>
298            end else if (pend_restart && !host_enable_i) begin
                        -2-  
299              pend_restart <= '0;
                 ==>
300            end else if (req_restart) begin
                        -3-  
301              pend_restart <= 1'b1;
                 ==>
302            end else if (log_start) begin
                        -4-  
303              pend_restart <= '0;
                 ==>
304            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T5,T12,T18
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3

308            if (!rst_ni) begin
               -1-  
309              auto_stop_q <= 1'b0;
                 ==>
310            end else begin
311              auto_stop_q <= auto_stop_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

361            unique case (state_q)
                      -1-  
362              // Idle: initial state, SDA is released (high), SCL is released if the
363              // bus is idle. Otherwise, if no STOP condition has been sent yet,
364              // continue pulling SCL low in host mode.
365              Idle : begin
366                sda_d = 1'b1;
367                if (trans_started) begin
                   -2-  
368                  host_idle_o = 1'b0;
                     ==>
369                  scl_d = 1'b0;
370                end else begin
371                  host_idle_o = 1'b1;
                     ==>
372                  scl_d = 1'b1;
373                end
374              end
375        
376              ///////////////
377              // HOST MODE //
378              ///////////////
379        
380              // SetupStart: SDA and SCL are released
381              SetupStart : begin
382                host_idle_o = 1'b0;
383                sda_d = 1'b1;
384                scl_d = 1'b1;
385                transmitting_o = 1'b1;
386                // If this is a restart, SCL was last low, and a target could be stretching the clock.
387                stretch_en = trans_started;
388                if (trans_started && !scl_i && scl_i_q) begin
                   -3-  
389                  // If this is a repeated Start, an early clock prevents issuing the symbol. If it's not
390                  // a repeated start, the FSM will just go back to Idle and wait for the bus to go free
391                  // again.
392                  ctrl_symbol_failed = 1'b1;
                     ==>
393                end else if (tcount_q == 20'd1) begin
                            -4-  
394                  log_start = 1'b1;
                     ==>
395                  event_cmd_complete_o = pend_restart;
396                end
                   MISSING_ELSE
                   ==>
397              end
398              // HoldStart: SDA is pulled low, SCL is released
399              HoldStart : begin
400                host_idle_o = 1'b0;
401                sda_d = 1'b0;
402                scl_d = 1'b1;
403                transmitting_o = 1'b1;
404                if (scl_i_q && !scl_i)  event_scl_interference_o = 1'b1;
                   -5-  
                   ==>
                   MISSING_ELSE
                   ==>
405              end
406              // ClockStart: SCL is pulled low, SDA stays low
407              ClockStart : begin
408                host_idle_o = 1'b0;
                   ==>
409                sda_d = 1'b0;
410                scl_d = 1'b0;
411                transmitting_o = 1'b1;
412              end
413              ClockLow : begin
414                host_idle_o = 1'b0;
415                if (pend_restart) begin
                   -6-  
416                  sda_d = 1'b1;
                     ==>
417                end else begin
418                  sda_d = fmt_byte_i[bit_index];
                     ==>
419                end
420                scl_d = 1'b0;
421                transmitting_o = 1'b1;
422              end
423              // ClockPulse: SCL is released, SDA keeps the indexed bit value
424              ClockPulse : begin
425                host_idle_o = 1'b0;
426                sda_d = fmt_byte_i[bit_index];
427                scl_d = 1'b1;
428                transmitting_o = 1'b1;
429                stretch_en = 1'b1;
430                if (scl_i_q && !scl_i)  event_scl_interference_o = 1'b1;
                   -7-  
                   ==>
                   MISSING_ELSE
                   ==>
431                if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                   -8-  
432                  // Unexpected Stop / Start
433                  event_sda_unstable_o = 1'b1;
                     ==>
434                end
                   MISSING_ELSE
                   ==>
435              end
436              // HoldBit: SCL is pulled low
437              HoldBit : begin
438                host_idle_o = 1'b0;
                   ==>
439                sda_d = fmt_byte_i[bit_index];
440                scl_d = 1'b0;
441                transmitting_o = 1'b1;
442              end
443              // ClockLowAck: SCL pulled low, SDA is released
444              ClockLowAck : begin
445                host_idle_o = 1'b0;
                   ==>
446                sda_d = 1'b1;
447                scl_d = 1'b0;
448              end
449              // ClockPulseAck: SCL is released
450              ClockPulseAck : begin
451                host_idle_o = 1'b0;
452                sda_d = 1'b1;
453                scl_d = 1'b1;
454                if (!scl_i_q && scl_i && sda_i && !fmt_flag_nak_ok_i) event_nak_o = 1'b1;
                   -9-  
                   ==>
                   MISSING_ELSE
                   ==>
455                stretch_en = 1'b1;
456                if (scl_i_q && !scl_i)  event_scl_interference_o = 1'b1;
                   -10-  
                   ==>
                   MISSING_ELSE
                   ==>
457                if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                   -11-  
458                  // Unexpected Stop / Start
459                  event_sda_unstable_o = 1'b1;
                     ==>
460                end
                   MISSING_ELSE
                   ==>
461              end
462              // HoldDevAck: SCL is pulled low
463              HoldDevAck : begin
464                host_idle_o = 1'b0;
                   ==>
465                sda_d = 1'b1;
466                scl_d = 1'b0;
467              end
468              // ReadClockLow: SCL is pulled low, SDA is released
469              ReadClockLow : begin
470                host_idle_o = 1'b0;
                   ==>
471                sda_d = 1'b1;
472                scl_d = 1'b0;
473              end
474              // ReadClockPulse: SCL is released, the indexed bit value is read off SDA
475              ReadClockPulse : begin
476                host_idle_o = 1'b0;
477                scl_d = 1'b1;
478                stretch_en = 1'b1;
479                if (scl_i_q && !scl_i)  event_scl_interference_o = 1'b1;
                   -12-  
                   ==>
                   MISSING_ELSE
                   ==>
480                if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                   -13-  
481                  // Unexpected Stop / Start
482                  event_sda_unstable_o = 1'b1;
                     ==>
483                end
                   MISSING_ELSE
                   ==>
484              end
485              // ReadHoldBit: SCL is pulled low
486              ReadHoldBit : begin
487                host_idle_o = 1'b0;
488                scl_d = 1'b0;
489                if (bit_index == '0 && tcount_q == 20'd1) begin
                   -14-  
490                  rx_fifo_wvalid_o = 1'b1;      // assert that rx_fifo has valid data
                     ==>
491                  rx_fifo_wdata_o = read_byte;  // transfer read data to rx_fifo
492                end
                   MISSING_ELSE
                   ==>
493              end
494              // HostClockLowAck: SCL pulled low, SDA is conditional
495              HostClockLowAck : begin
496                host_idle_o = 1'b0;
497                scl_d = 1'b0;
498                transmitting_o = 1'b1;
499        
500                // If it is the last byte of a read, send a NAK before the stop.
501                // Otherwise send the ack.
502                if (fmt_flag_read_continue_i) sda_d = 1'b0;
                   -15-  
                   ==>
503                else if (byte_index == 9'd1) sda_d = 1'b1;
                        -16-  
                   ==>
504                else sda_d = 1'b0;
                   ==>
505              end
506              // HostClockPulseAck: SCL is released
507              HostClockPulseAck : begin
508                host_idle_o = 1'b0;
509                if (fmt_flag_read_continue_i) sda_d = 1'b0;
                   -17-  
                   ==>
510                else if (byte_index == 9'd1) sda_d = 1'b1;
                        -18-  
                   ==>
511                else sda_d = 1'b0;
                   ==>
512                scl_d = 1'b1;
513                transmitting_o = 1'b1;
514                stretch_en = 1'b1;
515                if (scl_i_q && !scl_i)  event_scl_interference_o = 1'b1;
                   -19-  
                   ==>
                   MISSING_ELSE
                   ==>
516                if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                   -20-  
517                  // Unexpected Stop / Start
518                  event_sda_unstable_o = 1'b1;
                     ==>
519                end
                   MISSING_ELSE
                   ==>
520              end
521              // HostHoldBitAck: SCL is pulled low
522              HostHoldBitAck : begin
523                host_idle_o = 1'b0;
524                if (fmt_flag_read_continue_i) sda_d = 1'b0;
                   -21-  
                   ==>
525                else if (byte_index == 9'd1) sda_d = 1'b1;
                        -22-  
                   ==>
526                else sda_d = 1'b0;
                   ==>
527                scl_d = 1'b0;
528                transmitting_o = 1'b1;
529              end
530              // ClockStop: SCL is pulled low, SDA stays low
531              ClockStop : begin
532                host_idle_o = 1'b0;
                   ==>
533                sda_d = 1'b0;
534                scl_d = 1'b0;
535                transmitting_o = 1'b1;
536              end
537              // SetupStop: SDA is pulled low, SCL is released
538              SetupStop : begin
539                host_idle_o = 1'b0;
540                sda_d = 1'b0;
541                scl_d = 1'b1;
542                transmitting_o = 1'b1;
543                stretch_en = 1'b1;
544                if (!scl_i && scl_i_q) begin
                   -23-  
545                  // Failed to issue Stop before some other device could pull SCL low.
546                  ctrl_symbol_failed = 1'b1;
                     ==>
547                end
                   MISSING_ELSE
                   ==>
548              end
549              // HoldStop: SDA and SCL are released
550              HoldStop : begin
551                host_idle_o = 1'b0;
552                sda_d = 1'b1;
553                scl_d = 1'b1;
554                event_cmd_complete_o = 1'b1;
555                if (!sda_i && !scl_i) begin
                   -24-  
556                  // Failed to issue Stop before some other device could pull SCL low.
557                  ctrl_symbol_failed = 1'b1;
                     ==>
558                end else if (sda_i) begin
                            -25-  
559                  log_stop = 1'b1;
                     ==>
560                end
                   MISSING_ELSE
                   ==>
561              end
562              // Active: continue while keeping SCL low
563              Active : begin
564                host_idle_o = 1'b0;
                   ==>
565        
566                // If this is a transaction start, do not drive scl low
567                // since in the next state we will drive it high to initiate
568                // the start bit.
569                // If this is a restart, continue driving the clock low.
570                scl_d = fmt_flag_start_before_i && !trans_started;
571              end
572              // PopFmtFifo: populate fmt_fifo
573              PopFmtFifo : begin
574                host_idle_o = 1'b0;
575                if (fmt_flag_stop_after_i) scl_d = 1'b1;
                   -26-  
                   ==>
576                else scl_d = 1'b0;
                   ==>
577                fmt_fifo_rready_o = 1'b1;
578              end
579        
580              // default
581              default : begin
582                host_idle_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
SetupStart	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
SetupStart	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldStart	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
HoldStart	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockLow	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T18
ClockLow	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
ClockPulse	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulse	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T18,T19
ClockPulse	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T18
ClockPulseAck	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T18
ClockPulseAck	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T11
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T5,T14
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T14,T11
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T3,T5,T14
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T3,T5,T14
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T3,T4,T5
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

614            unique case (state_q)
                      -1-  
615              // Idle: initial state, SDA is released (high), and SCL is released if there is no ongoing
616              // transaction.
617              Idle : begin
618                if (host_enable_i) begin
                   -2-  
619                  if (unhandled_unexp_nak_i || unhandled_nak_timeout_i || halt_controller_i) begin
                     -3-  
620                    // If we are awaiting software to handle an unexpected NACK, halt the FSM here.
621                    // The current transaction does not end, and SCL remains in its current state.
622                    // Software typically should handle an unexpected NACK by either disabling the
623                    // controller (causing host_enable_i to fall) or by the following sequence:
624                    //   1. Clear and/or populate the FMT FIFO.
625                    //   2. Clear CONTROLLER_EVENTS.NACK
626                    // Note that if the timeout feature is enabled, the controller will be forced to
627                    // issue a Stop if software takes too long to address the NACK. A short timeout
628                    // could also be used to automatically issue a Stop whenever an unexpected NACK
629                    // occurs.
630                    // Note that we may also halt here on a bus timeout or if arbitration was lost, so
631                    // software may fix up the FIFOs before beginning a new transaction.
632                    if (trans_started && unhandled_nak_cnt_expired) begin
                       -4-  
633                      // If our timeout counter expires, generate a STOP condition automatically.
634                      auto_stop_d = 1'b1;
                         ==>
635                      state_d = ClockStop;
636                      load_tcount = 1'b1;
637                      tcount_sel = tClockStop;
638                    end
                       MISSING_ELSE
                       ==>
639                  end else if (fmt_fifo_rvalid_i) begin
                              -5-         
640                    if (trans_started || bus_free_i) begin
                       -6-  
641                      state_d = Active;
                         ==>
642                    end
                       MISSING_ELSE
                       ==>
643                  end
                     MISSING_ELSE
                     ==>
644                end else if (trans_started && !host_enable_i) begin
                            -7-  
645                    auto_stop_d = 1'b1;
                       ==>
646                    state_d = ClockStop;
647                    load_tcount = 1'b1;
648                    tcount_sel = tClockStop;
649                end
                   MISSING_ELSE
                   ==>
650              end
651        
652              ///////////////
653              // HOST MODE //
654              ///////////////
655        
656              // SetupStart: SDA and SCL are released
657              SetupStart : begin
658                if (!trans_started && !scl_i) begin
                   -8-  
659                  // This was the start of a transaction, but another device beat us to access. Go back to
660                  // Idle, and wait for the next turn.
661                  state_d = Idle;
                     ==>
662                end else if (trans_started && !scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                            -9-  
663                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
664                  state_d = SetupStart;
                     ==>
665                  load_tcount = 1'b1;
666                  // This double-counts the rise time, unfortunately.
667                  tcount_sel = tSetupStart;
668                end else if (trans_started && !scl_i && scl_i_q) begin
                            -10-  
669                  // Failed to issue repeated Start. Effectively lost arbitration.
670                  state_d = Idle;
                     ==>
671                end else if (tcount_q == 20'd1) begin
                            -11-  
672                  state_d = HoldStart;
                     ==>
673                  load_tcount = 1'b1;
674                  tcount_sel = tHoldStart;
675                end
                   MISSING_ELSE
                   ==>
676              end
677              // HoldStart: SDA is pulled low, SCL is released
678              HoldStart : begin
679                if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
                   -12-  
680                  state_d = ClockStart;
                     ==>
681                  load_tcount = 1'b1;
682                  tcount_sel = tClockStart;
683                end
                   MISSING_ELSE
                   ==>
684              end
685              // ClockStart: SCL is pulled low, SDA stays low
686              ClockStart : begin
687                if (tcount_q == 20'd1) begin
                   -13-  
688                  state_d = ClockLow;
                     ==>
689                  load_tcount = 1'b1;
690                  tcount_sel = tClockLow;
691                end
                   MISSING_ELSE
                   ==>
692              end
693              // ClockLow: SCL stays low, shift indexed bit onto SDA
694              ClockLow : begin
695                if (tcount_q == 20'd1) begin
                   -14-  
696                  load_tcount = 1'b1;
697                  if (pend_restart) begin
                     -15-  
698                    state_d = SetupStart;
                       ==>
699                    tcount_sel = tSetupStart;
700                  end else begin
701                    state_d = ClockPulse;
                       ==>
702                    tcount_sel = tClockPulse;
703                  end
704                end
                   MISSING_ELSE
                   ==>
705              end
706              // ClockPulse: SCL is released, SDA keeps the indexed bit value
707              ClockPulse : begin
708                if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                   -16-  
709                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
710                  load_tcount = 1'b1;
                     ==>
711                  tcount_sel = tClockHigh;
712                end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                            -17-  
713                  // Unexpected Stop / Start
714                  state_d = Idle;
                     ==>
715                end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
                            -18-  
716                  // Transition either when we finish counting our high period or
717                  // another controller pulls clock low.
718                  state_d = HoldBit;
                     ==>
719                  load_tcount = 1'b1;
720                  tcount_sel = tHoldBit;
721                end
                   MISSING_ELSE
                   ==>
722              end
723              // HoldBit: SCL is pulled low
724              HoldBit : begin
725                if (tcount_q == 20'd1) begin
                   -19-  
726                  load_tcount = 1'b1;
727                  tcount_sel = tClockLow;
728                  if (bit_index == '0) begin
                     -20-  
729                    state_d = ClockLowAck;
                       ==>
730                    bit_clr = 1'b1;
731                  end else begin
732                    state_d = ClockLow;
                       ==>
733                    bit_decr = 1'b1;
734                  end
735                end
                   MISSING_ELSE
                   ==>
736              end
737              // ClockLowAck: Target is allowed to drive ack back
738              // to host (dut)
739              ClockLowAck : begin
740                if (tcount_q == 20'd1) begin
                   -21-  
741                  state_d = ClockPulseAck;
                     ==>
742                  load_tcount = 1'b1;
743                  tcount_sel = tClockPulse;
744                end
                   MISSING_ELSE
                   ==>
745              end
746              // ClockPulseAck: SCL is released
747              ClockPulseAck : begin
748                if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                   -22-  
749                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
750                  load_tcount = 1'b1;
                     ==>
751                  tcount_sel = tClockHigh;
752                end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                            -23-  
753                  // Unexpected Stop / Start
754                  state_d = Idle;
                     ==>
755                end else begin
756                  if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
                     -24-  
757                    state_d = HoldDevAck;
                       ==>
758                    load_tcount = 1'b1;
759                    tcount_sel = tHoldBit;
760                  end
                     MISSING_ELSE
                     ==>
761                end
762              end
763              // HoldDevAck: SCL is pulled low
764              HoldDevAck : begin
765                if (tcount_q == 20'd1) begin
                   -25-  
766                  if (fmt_flag_stop_after_i) begin
                     -26-  
767                    state_d = ClockStop;
                       ==>
768                    load_tcount = 1'b1;
769                    tcount_sel = tClockStop;
770                  end else begin
771                    state_d = PopFmtFifo;
                       ==>
772                    load_tcount = 1'b1;
773                    tcount_sel = tNoDelay;
774                  end
775                end
                   MISSING_ELSE
                   ==>
776              end
777              // ReadClockLow: SCL is pulled low, SDA is released
778              ReadClockLow : begin
779                if (tcount_q == 20'd1) begin
                   -27-  
780                  state_d = ReadClockPulse;
                     ==>
781                  load_tcount = 1'b1;
782                  tcount_sel = tClockPulse;
783                end
                   MISSING_ELSE
                   ==>
784              end
785              // ReadClockPulse: SCL is released, the indexed bit value is read off SDA
786              ReadClockPulse : begin
787                if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                   -28-  
788                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
789                  load_tcount = 1'b1;
                     ==>
790                  tcount_sel = tClockHigh;
791                end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                            -29-  
792                  // Unexpected Stop / Start
793                  state_d = Idle;
                     ==>
794                end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
                            -30-  
795                  state_d = ReadHoldBit;
                     ==>
796                  load_tcount = 1'b1;
797                  tcount_sel = tHoldBit;
798                  shift_data_en = 1'b1; // SDA is sampled on the final clk_i cycle of the SCL pulse.
799                end
                   MISSING_ELSE
                   ==>
800              end
801              // ReadHoldBit: SCL is pulled low
802              ReadHoldBit : begin
803                if (tcount_q == 20'd1) begin
                   -31-  
804                  load_tcount = 1'b1;
805                  tcount_sel = tClockLow;
806                  if (bit_index == '0) begin
                     -32-  
807                    state_d = HostClockLowAck;
                       ==>
808                    bit_clr = 1'b1;
809                    read_byte_clr = 1'b1;
810                  end else begin
811                    state_d = ReadClockLow;
                       ==>
812                    bit_decr = 1'b1;
813                  end
814                end
                   MISSING_ELSE
                   ==>
815              end
816              // HostClockLowAck: SCL is pulled low, SDA is conditional based on
817              // byte position
818              HostClockLowAck : begin
819                if (tcount_q == 20'd1) begin
                   -33-  
820                  state_d = HostClockPulseAck;
                     ==>
821                  load_tcount = 1'b1;
822                  tcount_sel = tClockPulse;
823                end
                   MISSING_ELSE
                   ==>
824              end
825              // HostClockPulseAck: SCL is released
826              HostClockPulseAck : begin
827                if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                   -34-  
828                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
829                  load_tcount = 1'b1;
                     ==>
830                  tcount_sel = tClockHigh;
831                end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
                            -35-  
832                  // Unexpected Stop / Start
833                  state_d = Idle;
                     ==>
834                end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
                            -36-  
835                  state_d = HostHoldBitAck;
                     ==>
836                  load_tcount = 1'b1;
837                  tcount_sel = tHoldBit;
838                end
                   MISSING_ELSE
                   ==>
839              end
840              // HostHoldBitAck: SCL is pulled low
841              HostHoldBitAck : begin
842                if (tcount_q == 20'd1) begin
                   -37-  
843                  if (byte_index == 9'd1) begin
                     -38-  
844                    if (fmt_flag_stop_after_i) begin
                       -39-  
845                      state_d = ClockStop;
                         ==>
846                      load_tcount = 1'b1;
847                      tcount_sel = tClockStop;
848                    end else begin
849                      state_d = PopFmtFifo;
                         ==>
850                      load_tcount = 1'b1;
851                      tcount_sel = tNoDelay;
852                    end
853                  end else begin
854                    state_d = ReadClockLow;
                       ==>
855                    load_tcount = 1'b1;
856                    tcount_sel = tClockLow;
857                    byte_decr = 1'b1;
858                  end
859                end
                   MISSING_ELSE
                   ==>
860              end
861              // ClockStop: SCL is pulled low, SDA stays low
862              ClockStop : begin
863                if (tcount_q == 20'd1) begin
                   -40-  
864                  state_d = SetupStop;
                     ==>
865                  load_tcount = 1'b1;
866                  tcount_sel = tSetupStop;
867                end
                   MISSING_ELSE
                   ==>
868              end
869              // SetupStop: SDA is pulled low, SCL is released
870              SetupStop : begin
871                if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
                   -41-  
872                  // Saw stretching. Remain in this state and don't count down until we see SCL high.
873                  load_tcount = 1'b1;
                     ==>
874                  tcount_sel = tSetupStop;
875                end else if (!scl_i && scl_i_q) begin
                            -42-  
876                  // Failed to issue Stop before some other device could pull SCL low.
877                  state_d = Idle;
                     ==>
878                end else if (tcount_q == 20'd1) begin
                            -43-  
879                  state_d = HoldStop;
                     ==>
880                end
                   MISSING_ELSE
                   ==>
881              end
882              // HoldStop: SDA and SCL are released
883              HoldStop : begin
884                if (!sda_i && !scl_i) begin
                   -44-  
885                  // Failed to issue Stop before some other device could pull SCL low.
886                  state_d = Idle;
                     ==>
887                  auto_stop_d = 1'b0;
888                end else if (sda_i) begin
                            -45-  
889                  auto_stop_d = 1'b0;
890                  if (auto_stop_q) begin
                     -46-  
891                    // If this Stop symbol was generated automatically, go back to Idle.
892                    state_d = Idle;
                       ==>
893                    load_tcount = 1'b1;
894                    tcount_sel = tNoDelay;
895                  end else begin
896                    state_d = PopFmtFifo;
                       ==>
897                    load_tcount = 1'b1;
898                    tcount_sel = tNoDelay;
899                  end
900                end
                   MISSING_ELSE
                   ==>
901              end
902              // Active: continue while keeping SCL low
903              Active : begin
904                if (fmt_flag_read_bytes_i) begin
                   -47-  
905                  byte_clr = 1'b1;
                     ==>
906                  state_d = ReadClockLow;
907                  load_tcount = 1'b1;
908                  tcount_sel = tClockLow;
909                end else if (fmt_flag_start_before_i && !trans_started) begin
                            -48-  
910                  state_d = SetupStart;
                     ==>
911                  load_tcount = 1'b1;
912                  tcount_sel = tSetupStart;
913                end else begin
914                  state_d = ClockLow;
                     ==>
915                  load_tcount = 1'b1;
916                  req_restart = fmt_flag_start_before_i;
917                  tcount_sel = tClockLow;
918                end
919              end
920              // PopFmtFifo: pop fmt_fifo item
921              PopFmtFifo : begin
922                if (!host_enable_i && trans_started) begin
                   -49-  
923                  auto_stop_d = 1'b1;
                     ==>
924                  state_d = ClockStop;
925                  load_tcount = 1'b1;
926                  tcount_sel = tClockStop;
927                end else if (!host_enable_i || (fmt_fifo_depth_i == 7'h1) ||
                            -50-                            
928                             unhandled_unexp_nak_i || !trans_started) begin
929                  state_d = Idle;
                     ==>
930                  load_tcount = 1'b1;
931                  tcount_sel = tNoDelay;
932                end else begin
933                  state_d = Active;
                     ==>
934                  load_tcount = 1'b1;
935                  tcount_sel = tNoDelay;
936                end
937              end
938        
939              // default
940              default : begin
941                state_d = Idle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	-45-	-46-	-47-	-48-	-49-	-50-	Status	Tests
Idle	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T11
Idle	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T36,T37,T38
Idle	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
SetupStart	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
SetupStart	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
SetupStart	-	-	-	-	-	-	0	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
SetupStart	-	-	-	-	-	-	0	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldStart	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldStart	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockStart	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockStart	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T22
ClockLow	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T18
ClockLow	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockLow	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T18,T19
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T18
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T22
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T11
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T14
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Not Covered
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T3,T4,T5
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T5,T14
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T4,T5
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T4,T5
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

954            if (trans_started && (sda_interference_i || ctrl_symbol_failed)) begin
               -1-  
955              state_d = Idle;
                 ==>
956            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T18
0	Covered	T1,T2,T3

961            if (!rst_ni) begin
               -1-  
962              state_q <= Idle;
                 ==>
963            end else begin
964              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_controller_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SclOutputGlitch_A	390033414	3479573	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390033414	3479573	0	0
T3	14401	586	0	0
T4	5432	19	0	0
T5	14001	261	0	0
T6	7532	0	0	0
T7	20083	0	0	0
T8	26088	0	0	0
T9	12628	0	0	0
T10	78164	0	0	0
T11	0	1439	0	0
T14	0	396	0	0
T22	0	46	0	0
T29	0	1329	0	0
T41	0	811	0	0
T43	0	586	0	0
T44	0	28	0	0
T45	48225	0	0	0
T46	133362	0	0	0