Line Coverage for Instance : tb.dut.u_reg.u_timing1_t_f
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing1_t_f
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing1_t_f
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing2_tsu_sta
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing2_tsu_sta
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing2_tsu_sta
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing2_thd_sta
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing2_thd_sta
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing2_thd_sta
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing3_tsu_dat
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing3_tsu_dat
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing3_tsu_dat
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing3_thd_dat
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing3_thd_dat
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing3_thd_dat
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing4_tsu_sto
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing4_tsu_sto
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing4_tsu_sto
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timing4_t_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timing4_t_buf
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timing4_t_buf
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_mode
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_mode
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_mode
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T3 T5 T6
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T3 T5 T6
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T5,T6 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_id_address0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_id_address0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_id_address0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_id_mask0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_id_mask0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_id_mask0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_id_address1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_id_address1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_id_address1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_id_mask1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_id_mask1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_id_mask1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_txdata
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_txdata
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_txdata
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_host_timeout_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T6 T7
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T5 T6 T7
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_host_timeout_ctrl
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_host_timeout_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T63 T64 T60
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T63 T64 T60
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_val
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T63,T64,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T63,T64,T60 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T63,T64,T60 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T63 T64 T60
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T63 T64 T60
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_en
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T63,T64,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_target_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T63,T64,T60 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T63,T64,T60 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_target_nack_count
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T63 T64 T60
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 1/1 assign qs = de && we ? d : q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_target_nack_count
| Total | Covered | Percent |
Conditions | 7 | 5 | 71.43 |
Logical | 7 | 5 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T63,T64,T60 |
LINE 70
EXPRESSION ((de && we) ? d : q)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 70
SUB-EXPRESSION (de && we)
-1 -2
-1- | -2- | Status | Tests |
0 | 1 | Covered | T63,T64,T60 |
1 | 0 | Covered | T63,T64,T60 |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_target_nack_count
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
64 |
2 |
2 |
100.00 |
TERNARY |
70 |
2 |
1 |
50.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T63,T64,T60 |
0 |
Covered |
T1,T2,T3 |
70 assign qs = de && we ? d : q;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T63,T64,T60 |
0 |
0 |
Covered |
T1,T2,T3 |