Module Definition
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Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.48 100.00 100.00 93.91 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.39 97.14 89.39 97.22 72.02 94.08 98.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 87.60 96.10 83.55 72.02 91.30 95.04
i2c_csr_assert 93.75 93.75
tlul_assert_device 100.00 100.00
u_reg 98.69 98.59 97.25 100.00 97.58 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00


68                      
69         1/1            assign alert_test = {
           Tests:       T1 T2 T3 
70                          reg2hw.alert_test.q &
71                          reg2hw.alert_test.qe
72                        };
73                      
74                        for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
75                          prim_alert_sender #(
76                            .AsyncOn(AlertAsyncOn[i]),
77                            .IsFatal(1'b1)
78                          ) u_prim_alert_sender (
79                            .clk_i,
80                            .rst_ni,
81                            .alert_test_i  ( alert_test[i] ),
82                            .alert_req_i   ( alerts[0]     ),
83                            .alert_ack_o   (               ),
84                            .alert_state_o (               ),
85                            .alert_rx_i    ( alert_rx_i[i] ),
86                            .alert_tx_o    ( alert_tx_o[i] )
87                          );
88                        end
89                      
90                        logic scl_int;
91                        logic sda_int;
92                      
93                        i2c_core #(
94                          .InputDelayCycles(InputDelayCycles)
95                        ) i2c_core (
96                          .clk_i,
97                          .rst_ni,
98                          .ram_cfg_i,
99                      
100                         .reg2hw,
101                         .hw2reg,
102                     
103                         .scl_i(cio_scl_i),
104                         .scl_o(scl_int),
105                         .sda_i(cio_sda_i),
106                         .sda_o(sda_int),
107                     
108                         .intr_fmt_threshold_o,
109                         .intr_rx_threshold_o,
110                         .intr_acq_threshold_o,
111                         .intr_rx_overflow_o,
112                         .intr_controller_halt_o,
113                         .intr_scl_interference_o,
114                         .intr_sda_interference_o,
115                         .intr_stretch_timeout_o,
116                         .intr_sda_unstable_o,
117                         .intr_cmd_complete_o,
118                         .intr_tx_stretch_o,
119                         .intr_tx_threshold_o,
120                         .intr_acq_stretch_o,
121                         .intr_unexp_stop_o,
122                         .intr_host_timeout_o
123                       );
124                     
125                       // For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
126                       // Asserting scl or sda high should be equivalent to a tri-state output.
127                       // The output, when enabled, should only assert low.
128                     
129                       assign cio_scl_o = 1'b0;
130                       assign cio_sda_o = 1'b0;
131                     
132        1/1            assign cio_scl_en_o = ~scl_int;
           Tests:       T1 T2 T3 
133        1/1            assign cio_sda_en_o = ~sda_int;
           Tests:       T1 T2 T3 
Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT98,T99,T100
10CoveredT1,T2,T3
11CoveredT98,T99,T100
Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 51 45 88.24
Total Bits 394 370 93.91
Total Bits 0->1 197 185 93.91
Total Bits 1->0 197 185 93.91

Ports 51 45 88.24
Port Bits 394 370 93.91
Port Bits 0->1 197 185 93.91
Port Bits 1->0 197 185 93.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T8,T174,T184 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T103,T185,T186 Yes T103,T185,T186 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T174,T98,T99 Yes T174,T98,T99 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T174,T98,T99 Yes T174,T98,T99 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T1,T2,T4 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T2,T5,T6 Yes T2,T4,T5 OUTPUT
intr_rx_threshold_o Yes Yes T2,T30,T31 Yes T2,T30,T31 OUTPUT
intr_acq_threshold_o Yes Yes T42,T169,T155 Yes T42,T169,T155 OUTPUT
intr_rx_overflow_o Yes Yes T31,T33,T102 Yes T31,T33,T102 OUTPUT
intr_controller_halt_o Yes Yes T8,T11,T12 Yes T8,T11,T12 OUTPUT
intr_scl_interference_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_sda_interference_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_stretch_timeout_o Yes Yes T2,T4,T6 Yes T2,T4,T6 OUTPUT
intr_sda_unstable_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_cmd_complete_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
intr_tx_stretch_o Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
intr_tx_threshold_o Yes Yes T8,T10,T43 Yes T2,T4,T5 OUTPUT
intr_acq_stretch_o Yes Yes T42,T44,T45 Yes T42,T44,T45 OUTPUT
intr_unexp_stop_o Yes Yes T42,T50,T183 Yes T42,T50,T183 OUTPUT
intr_host_timeout_o Yes Yes T72,T75,T76 Yes T72,T75,T76 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 389927877 389774674 0 0
CioSclEnKnownO_A 389927877 389774674 0 0
CioSclKnownO_A 389927877 389774674 0 0
CioSdaEnKnownO_A 389927877 389774674 0 0
CioSdaKnownO_A 389927877 389774674 0 0
FpvSecCmRegWeOnehotCheck_A 389927877 70 0 0
IntrAcqStretchKnownO_A 389927877 389774674 0 0
IntrAcqWtmkKnownO_A 389927877 389774674 0 0
IntrCommandCompleteKnownO_A 389927877 389774674 0 0
IntrControllerHaltKnownO_A 389927877 389774674 0 0
IntrFmtWtmkKnownO_A 389927877 389774674 0 0
IntrHostTimeoutKnownO_A 389927877 389774674 0 0
IntrRxOflwKnownO_A 389927877 389774674 0 0
IntrRxWtmkKnownO_A 389927877 389774674 0 0
IntrSclInterfKnownO_A 389927877 389774674 0 0
IntrSdaInterfKnownO_A 389927877 389774674 0 0
IntrSdaUnstableKnownO_A 389927877 389774674 0 0
IntrStretchTimeoutKnownO_A 389927877 389774674 0 0
IntrTxStretchKnownO_A 389927877 389774674 0 0
IntrTxWtmkKnownO_A 389927877 389774674 0 0
IntrUnexpStopKnownO_A 389927877 389774674 0 0
TlAReadyKnownO_A 389927877 389774674 0 0
TlDValidKnownO_A 389927877 389774674 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 70 0 0
T34 4073 0 0 0
T50 187538 0 0 0
T62 48952 0 0 0
T77 1999 0 0 0
T98 1482 0 0 0
T125 0 20 0 0
T154 16739 0 0 0
T155 405127 0 0 0
T156 47547 0 0 0
T157 77159 0 0 0
T174 3916 10 0 0
T184 0 10 0 0
T187 0 20 0 0
T188 0 10 0 0

IntrAcqStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389927877 389774674 0 0
T1 2144 2055 0 0
T2 141243 141187 0 0
T3 15679 15628 0 0
T4 24413 24336 0 0
T5 14990 14892 0 0
T6 11679 11592 0 0
T7 97119 97029 0 0
T8 12797 12402 0 0
T9 77103 77043 0 0
T10 73415 73333 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%