Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	390652947	0	0	0
ctrl_rd_A	390652947	3615	0	0
host_fifo_config_rd_A	390652947	6069	0	0
host_nack_handler_timeout_rd_A	390652947	2341	0	0
host_timeout_ctrl_rd_A	390652947	2465	0	0
intr_enable_rd_A	390652947	5940	0	0
ovrd_rd_A	390652947	2118	0	0
target_fifo_config_rd_A	390652947	2618	0	0
target_id_rd_A	390652947	3221	0	0
target_timeout_ctrl_rd_A	390652947	2440	0	0
timeout_ctrl_rd_A	390652947	2476	0	0
timing0_rd_A	390652947	2478	0	0
timing1_rd_A	390652947	2439	0	0
timing2_rd_A	390652947	2504	0	0
timing3_rd_A	390652947	2540	0	0
timing4_rd_A	390652947	2484	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	3615	0	0
T103	4658	16	0	0
T104	2366	38	0	0
T105	1241	4	0	0
T106	6300	60	0	0
T107	2023	7	0	0
T108	2621	17	0	0
T109	2190	10	0	0
T110	13460	177	0	0
T111	7539	6	0	0
T112	13621	278	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	6069	0	0
T56	894546	0	0	0
T113	416513	189	0	0
T114	0	119	0	0
T115	0	108	0	0
T116	0	140	0	0
T117	0	111	0	0
T118	0	119	0	0
T119	0	123	0	0
T120	0	102	0	0
T121	0	162	0	0
T122	0	124	0	0
T123	45267	0	0	0
T124	14695	0	0	0
T125	5413	0	0	0
T126	49158	0	0	0
T127	932	0	0	0
T128	53835	0	0	0
T129	2044	0	0	0
T130	17629	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2341	0	0
T103	4658	9	0	0
T104	2366	10	0	0
T105	1241	6	0	0
T106	6300	55	0	0
T107	2023	3	0	0
T108	2621	8	0	0
T109	2190	6	0	0
T110	13460	56	0	0
T111	7539	21	0	0
T112	13621	107	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2465	0	0
T103	4658	12	0	0
T104	2366	13	0	0
T105	1241	3	0	0
T106	6300	66	0	0
T107	2023	11	0	0
T108	2621	9	0	0
T109	2190	1	0	0
T110	13460	49	0	0
T111	7539	12	0	0
T112	13621	82	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	5940	0	0
T36	0	25	0	0
T84	106130	0	0	0
T103	0	2	0	0
T104	0	111	0	0
T131	140900	28	0	0
T132	0	21	0	0
T133	0	32	0	0
T134	0	15	0	0
T135	0	18	0	0
T136	0	11	0	0
T137	0	11	0	0
T138	9921	0	0	0
T139	118825	0	0	0
T140	38685	0	0	0
T141	249942	0	0	0
T142	69038	0	0	0
T143	54030	0	0	0
T144	8880	0	0	0
T145	47274	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2118	0	0
T31	171099	0	0	0
T34	4073	0	0	0
T50	187538	0	0	0
T75	952549	0	0	0
T77	1999	42	0	0
T129	0	58	0	0
T146	0	45	0	0
T147	0	34	0	0
T148	0	42	0	0
T149	0	60	0	0
T150	0	49	0	0
T151	0	48	0	0
T152	0	57	0	0
T153	0	21	0	0
T154	16739	0	0	0
T155	405127	0	0	0
T156	47547	0	0	0
T157	77159	0	0	0
T158	13677	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2618	0	0
T103	4658	14	0	0
T104	2366	8	0	0
T105	1241	6	0	0
T106	6300	64	0	0
T107	2023	7	0	0
T108	2621	10	0	0
T109	2190	8	0	0
T110	13460	65	0	0
T111	7539	6	0	0
T112	13621	126	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	3221	0	0
T103	4658	5	0	0
T104	2366	22	0	0
T106	6300	89	0	0
T107	2023	8	0	0
T108	2621	8	0	0
T109	2190	5	0	0
T110	13460	124	0	0
T111	7539	10	0	0
T112	13621	249	0	0
T159	4867	56	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2440	0	0
T103	4658	15	0	0
T104	2366	22	0	0
T105	1241	1	0	0
T106	6300	42	0	0
T107	2023	6	0	0
T108	2621	14	0	0
T109	2190	1	0	0
T110	13460	58	0	0
T111	7539	3	0	0
T112	13621	86	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2476	0	0
T103	4658	9	0	0
T104	2366	17	0	0
T105	1241	2	0	0
T106	6300	48	0	0
T107	2023	4	0	0
T108	2621	17	0	0
T109	2190	17	0	0
T110	13460	64	0	0
T111	7539	27	0	0
T112	13621	133	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2478	0	0
T103	4658	9	0	0
T104	2366	8	0	0
T105	1241	9	0	0
T106	6300	63	0	0
T107	2023	8	0	0
T108	2621	19	0	0
T109	2190	7	0	0
T110	13460	29	0	0
T111	7539	20	0	0
T112	13621	125	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2439	0	0
T103	4658	4	0	0
T104	2366	15	0	0
T105	1241	1	0	0
T106	6300	62	0	0
T107	2023	1	0	0
T108	2621	6	0	0
T109	2190	3	0	0
T110	13460	80	0	0
T111	7539	8	0	0
T112	13621	130	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2504	0	0
T103	4658	17	0	0
T104	2366	10	0	0
T105	1241	9	0	0
T106	6300	68	0	0
T107	2023	8	0	0
T108	2621	17	0	0
T109	2190	13	0	0
T110	13460	60	0	0
T111	7539	1	0	0
T112	13621	131	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2540	0	0
T103	4658	14	0	0
T104	2366	12	0	0
T105	1241	9	0	0
T106	6300	66	0	0
T107	2023	6	0	0
T108	2621	19	0	0
T109	2190	6	0	0
T110	13460	70	0	0
T111	7539	21	0	0
T112	13621	140	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390652947	2484	0	0
T103	4658	18	0	0
T104	2366	16	0	0
T106	6300	50	0	0
T107	2023	14	0	0
T108	2621	12	0	0
T109	2190	12	0	0
T110	13460	52	0	0
T111	7539	7	0	0
T112	13621	123	0	0
T159	4867	83	0	0