Line Coverage for Module :
i2c_core
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 133 | 130 | 97.74 |
| CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 215 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 216 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 220 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 223 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 226 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 227 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 233 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 253 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 255 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| ALWAYS | 262 | 5 | 5 | 100.00 |
| ALWAYS | 274 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 306 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 311 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 312 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 319 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 323 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 337 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 338 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 340 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 344 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 345 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 348 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 360 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 361 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 362 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 363 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 364 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 365 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 366 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 367 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 368 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 422 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 423 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| ALWAYS | 459 | 5 | 5 | 100.00 |
| ALWAYS | 469 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 485 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 488 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 489 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 850 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 852 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 854 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 856 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 857 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 865 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 868 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 870 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 871 | 1 | 1 | 100.00 |
211
212 1/1 assign hw2reg.status.fmtfull.d = ~fmt_fifo_wready;
Tests: T1 T2 T3
213 1/1 assign hw2reg.status.rxfull.d = ~rx_fifo_wready;
Tests: T1 T2 T3
214 1/1 assign hw2reg.status.fmtempty.d = ~fmt_fifo_rvalid;
Tests: T1 T2 T3
215 1/1 assign hw2reg.status.hostidle.d = host_idle;
Tests: T1 T2 T3
216 1/1 assign hw2reg.status.targetidle.d = target_idle;
Tests: T1 T2 T3
217 1/1 assign hw2reg.status.rxempty.d = ~rx_fifo_rvalid;
Tests: T1 T2 T3
218 1/1 assign hw2reg.status.ack_ctrl_stretch.d = target_ack_ctrl_stretching;
Tests: T1 T2 T3
219
220 1/1 assign hw2reg.rdata.d = rx_fifo_rdata;
Tests: T1 T2 T3
221 1/1 assign hw2reg.host_fifo_status.fmtlvl.d = MaxFifoDepthW'(fmt_fifo_depth);
Tests: T1 T2 T3
222 1/1 assign hw2reg.host_fifo_status.rxlvl.d = MaxFifoDepthW'(rx_fifo_depth);
Tests: T1 T2 T3
223 1/1 assign hw2reg.val.scl_rx.d = scl_rx_val;
Tests: T1 T2 T3
224 1/1 assign hw2reg.val.sda_rx.d = sda_rx_val;
Tests: T1 T2 T3
225
226 1/1 assign hw2reg.status.txfull.d = ~tx_fifo_wready;
Tests: T1 T2 T3
227 1/1 assign hw2reg.status.acqfull.d = acq_fifo_full;
Tests: T1 T2 T3
228 1/1 assign hw2reg.status.txempty.d = ~tx_fifo_rvalid;
Tests: T1 T2 T3
229 1/1 assign hw2reg.status.acqempty.d = ~acq_fifo_rvalid;
Tests: T1 T2 T3
230 1/1 assign hw2reg.target_fifo_status.txlvl.d = MaxFifoDepthW'(tx_fifo_depth);
Tests: T1 T2 T3
231 1/1 assign hw2reg.target_fifo_status.acqlvl.d = MaxFifoDepthW'(acq_fifo_depth);
Tests: T1 T2 T3
232 1/1 assign hw2reg.acqdata.abyte.d = acq_fifo_rdata[7:0];
Tests: T1 T2 T3
233 1/1 assign hw2reg.acqdata.signal.d = acq_fifo_rdata[ACQ_FIFO_WIDTH-1:8];
Tests: T1 T2 T3
234
235 // Add one to the target NACK count if this target has sent a NACK and if
236 // counter has not saturated.
237 1/1 assign hw2reg.target_nack_count.de = event_target_nack && (reg2hw.target_nack_count.q < 8'hFF);
Tests: T1 T2 T3
238 1/1 assign hw2reg.target_nack_count.d = reg2hw.target_nack_count.q + 1;
Tests: T1 T2 T3
239
240 1/1 assign override = reg2hw.ovrd.txovrden;
Tests: T1 T2 T3
241
242 1/1 assign scl_o = override ? reg2hw.ovrd.sclval : scl_out_fsm;
Tests: T1 T2 T3
243 1/1 assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;
Tests: T1 T2 T3
244
245 1/1 assign host_enable = reg2hw.ctrl.enablehost.q;
Tests: T1 T2 T3
246 1/1 assign target_enable = reg2hw.ctrl.enabletarget.q;
Tests: T1 T2 T3
247 1/1 assign line_loopback = reg2hw.ctrl.llpbk.q;
Tests: T1 T2 T3
248
249 1/1 assign event_cmd_complete = event_controller_cmd_complete | event_target_cmd_complete;
Tests: T1 T2 T3
250
251 // Target loopback simply plays back whatever is received from the external host
252 // back to it.
253 1/1 assign target_loopback = target_enable & line_loopback;
Tests: T1 T2 T3
254
255 1/1 assign target_address0 = reg2hw.target_id.address0.q;
Tests: T1 T2 T3
256 1/1 assign target_mask0 = reg2hw.target_id.mask0.q;
Tests: T1 T2 T3
257 1/1 assign target_address1 = reg2hw.target_id.address1.q;
Tests: T1 T2 T3
258 1/1 assign target_mask1 = reg2hw.target_id.mask1.q;
Tests: T1 T2 T3
259
260 // Flop I2C bus outputs
261 always_ff @(posedge clk_i or negedge rst_ni) begin
262 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
263 1/1 scl_out_fsm <= 1'b1;
Tests: T1 T2 T3
264 1/1 sda_out_fsm <= 1'b1;
Tests: T1 T2 T3
265 end else begin
266 // Drive 0 if any FSM requests it.
267 1/1 scl_out_fsm <= scl_out_controller_fsm & scl_out_target_fsm;
Tests: T1 T2 T3
268 1/1 sda_out_fsm <= sda_out_controller_fsm & sda_out_target_fsm;
Tests: T1 T2 T3
269 end
270 end
271
272 // Sample scl_i and sda_i at system clock
273 always_ff @ (posedge clk_i or negedge rst_ni) begin : rx_oversampling
274 1/1 if(!rst_ni) begin
Tests: T1 T2 T3
275 1/1 scl_rx_val <= 16'h0;
Tests: T1 T2 T3
276 1/1 sda_rx_val <= 16'h0;
Tests: T1 T2 T3
277 end else begin
278 1/1 scl_rx_val <= {scl_rx_val[14:0], scl_i};
Tests: T1 T2 T3
279 1/1 sda_rx_val <= {sda_rx_val[14:0], sda_i};
Tests: T1 T2 T3
280 end
281 end
282
283 1/1 assign thigh = reg2hw.timing0.thigh.q;
Tests: T1 T2 T3
284 1/1 assign tlow = reg2hw.timing0.tlow.q;
Tests: T1 T2 T3
285 1/1 assign t_r = 13'(reg2hw.timing1.t_r.q);
Tests: T1 T2 T3
286 1/1 assign t_f = 13'(reg2hw.timing1.t_f.q);
Tests: T1 T2 T3
287 1/1 assign tsu_sta = reg2hw.timing2.tsu_sta.q;
Tests: T1 T2 T3
288 1/1 assign thd_sta = reg2hw.timing2.thd_sta.q;
Tests: T1 T2 T3
289 1/1 assign tsu_dat = 13'(reg2hw.timing3.tsu_dat.q);
Tests: T1 T2 T3
290 1/1 assign thd_dat = reg2hw.timing3.thd_dat.q;
Tests: T1 T2 T3
291 1/1 assign tsu_sto = reg2hw.timing4.tsu_sto.q;
Tests: T1 T2 T3
292 1/1 assign t_buf = reg2hw.timing4.t_buf.q;
Tests: T1 T2 T3
293 1/1 assign bus_active_timeout = reg2hw.timeout_ctrl.val.q;
Tests: T1 T2 T3
294 1/1 assign stretch_timeout_enable = reg2hw.timeout_ctrl.en.q &&
Tests: T1 T2 T3
295 (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode);
296 1/1 assign bus_timeout_enable = reg2hw.timeout_ctrl.en.q &&
Tests: T1 T2 T3
297 (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode);
298 1/1 assign host_timeout = reg2hw.host_timeout_ctrl.q;
Tests: T1 T2 T3
299 1/1 assign nack_timeout = reg2hw.target_timeout_ctrl.val.q;
Tests: T1 T2 T3
300 1/1 assign nack_timeout_en = reg2hw.target_timeout_ctrl.en.q;
Tests: T1 T2 T3
301 1/1 assign host_nack_handler_timeout = reg2hw.host_nack_handler_timeout.val.q;
Tests: T1 T2 T3
302 1/1 assign host_nack_handler_timeout_en = reg2hw.host_nack_handler_timeout.en.q;
Tests: T1 T2 T3
303 1/1 assign target_ack_ctrl_sw_nack = reg2hw.target_ack_ctrl.nack.qe &
Tests: T1 T2 T3
304 reg2hw.target_ack_ctrl.nack.q;
305
306 1/1 assign i2c_fifo_rxrst = reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe;
Tests: T1 T2 T3
307 1/1 assign i2c_fifo_fmtrst = reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe;
Tests: T1 T2 T3
308 1/1 assign i2c_fifo_rx_thresh = reg2hw.host_fifo_config.rx_thresh.q;
Tests: T1 T2 T3
309 1/1 assign i2c_fifo_fmt_thresh = reg2hw.host_fifo_config.fmt_thresh.q;
Tests: T1 T2 T3
310
311 1/1 assign i2c_fifo_txrst = reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe;
Tests: T1 T2 T3
312 1/1 assign i2c_fifo_acqrst = reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe;
Tests: T1 T2 T3
313 1/1 assign i2c_fifo_tx_thresh = reg2hw.target_fifo_config.tx_thresh.q;
Tests: T1 T2 T3
314 1/1 assign i2c_fifo_acq_thresh = reg2hw.target_fifo_config.acq_thresh.q;
Tests: T1 T2 T3
315
316 // FMT FIFO level below programmed threshold?
317 1/1 assign fmt_lt_threshold = (MaxFifoDepthW'(fmt_fifo_depth) < i2c_fifo_fmt_thresh);
Tests: T1 T2 T3
318 // Rx FIFO level above programmed threshold?
319 1/1 assign rx_gt_threshold = (MaxFifoDepthW'(rx_fifo_depth) > i2c_fifo_rx_thresh);
Tests: T1 T2 T3
320 // Tx FIFO level below programmed threshold?
321 1/1 assign tx_lt_threshold = (MaxFifoDepthW'(tx_fifo_depth) < i2c_fifo_tx_thresh);
Tests: T1 T2 T3
322 // ACQ FIFO level above programmed threshold?
323 1/1 assign acq_gt_threshold = (MaxFifoDepthW'(acq_fifo_depth) > i2c_fifo_acq_thresh);
Tests: T1 T2 T3
324
325 1/1 assign event_rx_overflow = rx_fifo_wvalid & ~rx_fifo_wready;
Tests: T1 T2 T3
326 1/1 assign event_acq_stretch = acq_fifo_full || target_ack_ctrl_stretching;
Tests: T1 T2 T3
327
328 // The fifo write enable is controlled by fbyte, start, stop, read, rcont,
329 // and nakok field qe bits.
330 // When all qe bits are asserted, fdata is injected into the fifo.
331 1/1 assign fmt_fifo_wvalid = reg2hw.fdata.fbyte.qe &
Tests: T1 T2 T3
332 reg2hw.fdata.start.qe &
333 reg2hw.fdata.stop.qe &
334 reg2hw.fdata.readb.qe &
335 reg2hw.fdata.rcont.qe &
336 reg2hw.fdata.nakok.qe;
337 1/1 assign fmt_fifo_wdata[7:0] = reg2hw.fdata.fbyte.q;
Tests: T1 T2 T3
338 1/1 assign fmt_fifo_wdata[8] = reg2hw.fdata.start.q;
Tests: T1 T2 T3
339 1/1 assign fmt_fifo_wdata[9] = reg2hw.fdata.stop.q;
Tests: T1 T2 T3
340 1/1 assign fmt_fifo_wdata[10] = reg2hw.fdata.readb.q;
Tests: T1 T2 T3
341 1/1 assign fmt_fifo_wdata[11] = reg2hw.fdata.rcont.q;
Tests: T1 T2 T3
342 1/1 assign fmt_fifo_wdata[12] = reg2hw.fdata.nakok.q;
Tests: T1 T2 T3
343
344 1/1 assign fmt_byte = fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0;
Tests: T1 T2 T3
345 1/1 assign fmt_flag_start_before = fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0;
Tests: T1 T2 T3
346 1/1 assign fmt_flag_stop_after = fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0;
Tests: T1 T2 T3
347 1/1 assign fmt_flag_read_bytes = fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0;
Tests: T1 T2 T3
348 1/1 assign fmt_flag_read_continue = fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0;
Tests: T1 T2 T3
349 1/1 assign fmt_flag_nak_ok = fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0;
Tests: T1 T2 T3
350
351 // Operating this HWIP as a controller-transmitter, the addressed Target device
352 // may NACK our bytes. In Byte-Formatted Programming Mode, each FDATA format indicator
353 // can set the 'NAKOK' bit to ignore the Target's NACK and proceed to the next item in
354 // the FMTFIFO. If 'NAKOK' is not set, the 'controller_halt' interrupt is asserted, and the FSM
355 // halts until software intervenes. In addition, the 'controller_events.nack' status bit is set.
356 // To acknowledge the 'NACK', software should clear the status bit by writing 1 to it in the
357 // CONTROLLER_EVENTS register.
358 1/1 assign unhandled_unexp_nak = reg2hw.controller_events.nack.q;
Tests: T1 T2 T3
359
360 1/1 assign unused_rx_thr_qe = reg2hw.host_fifo_config.rx_thresh.qe;
Tests: T1 T2 T3
361 1/1 assign unused_fmt_thr_qe = reg2hw.host_fifo_config.fmt_thresh.qe;
Tests: T1 T2 T3
362 1/1 assign unused_tx_thr_qe = reg2hw.target_fifo_config.tx_thresh.qe;
Tests: T1 T2 T3
363 1/1 assign unused_acq_thr_qe = reg2hw.target_fifo_config.acq_thresh.qe;
Tests: T1 T2 T3
364 0/1 ==> assign unused_rx_fifo_rdata_q = reg2hw.rdata.q;
365 0/1 ==> assign unused_acq_fifo_adata_q = reg2hw.acqdata.abyte.q;
366 0/1 ==> assign unused_acq_fifo_signal_q = reg2hw.acqdata.signal.q;
367 1/1 assign unused_alert_test_qe = reg2hw.alert_test.qe;
Tests: T99 T100 T101
368 1/1 assign unused_alert_test_q = reg2hw.alert_test.q;
Tests: T1 T2 T3
369
370 i2c_fifos u_fifos (
371 .clk_i,
372 .rst_ni,
373 .ram_cfg_i,
374
375 .fmt_fifo_clr_i (i2c_fifo_fmtrst),
376 .fmt_fifo_depth_o (fmt_fifo_depth),
377 .fmt_fifo_wvalid_i(fmt_fifo_wvalid),
378 .fmt_fifo_wready_o(fmt_fifo_wready),
379 .fmt_fifo_wdata_i (fmt_fifo_wdata),
380 .fmt_fifo_rvalid_o(fmt_fifo_rvalid),
381 .fmt_fifo_rready_i(fmt_fifo_rready),
382 .fmt_fifo_rdata_o (fmt_fifo_rdata),
383
384 .rx_fifo_clr_i (i2c_fifo_rxrst),
385 .rx_fifo_depth_o (rx_fifo_depth),
386 .rx_fifo_wvalid_i(rx_fifo_wvalid),
387 .rx_fifo_wready_o(rx_fifo_wready),
388 .rx_fifo_wdata_i (rx_fifo_wdata),
389 .rx_fifo_rvalid_o(rx_fifo_rvalid),
390 .rx_fifo_rready_i(rx_fifo_rready),
391 .rx_fifo_rdata_o (rx_fifo_rdata),
392
393 .tx_fifo_clr_i (i2c_fifo_txrst),
394 .tx_fifo_depth_o (tx_fifo_depth),
395 .tx_fifo_wvalid_i(tx_fifo_wvalid),
396 .tx_fifo_wready_o(tx_fifo_wready),
397 .tx_fifo_wdata_i (tx_fifo_wdata),
398 .tx_fifo_rvalid_o(tx_fifo_rvalid),
399 .tx_fifo_rready_i(tx_fifo_rready),
400 .tx_fifo_rdata_o (tx_fifo_rdata),
401
402 .acq_fifo_clr_i (i2c_fifo_acqrst),
403 .acq_fifo_depth_o (acq_fifo_depth),
404 .acq_fifo_wvalid_i(acq_fifo_wvalid),
405 .acq_fifo_wready_o(),
406 .acq_fifo_wdata_i (acq_fifo_wdata),
407 .acq_fifo_rvalid_o(acq_fifo_rvalid),
408 .acq_fifo_rready_i(acq_fifo_rready),
409 .acq_fifo_rdata_o (acq_fifo_rdata)
410 );
411
412 1/1 assign rx_fifo_rready = reg2hw.rdata.re;
Tests: T2 T6 T7
413
414 // Need to add a valid qualification to write only payload bytes
415 logic valid_target_lb_wr;
416 i2c_acq_byte_id_e acq_type;
417 1/1 assign acq_type = i2c_acq_byte_id_e'(acq_fifo_rdata[ACQ_FIFO_WIDTH-1:8]);
Tests: T1 T2 T3
418
419 1/1 assign valid_target_lb_wr = target_enable & (acq_type == AcqData);
Tests: T1 T2 T3
420
421 // only write into tx fifo if it's payload
422 1/1 assign tx_fifo_wvalid = target_loopback ? acq_fifo_rvalid & valid_target_lb_wr : reg2hw.txdata.qe;
Tests: T1 T2 T3
423 1/1 assign tx_fifo_wdata = target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q;
Tests: T1 T2 T3
424
425 // During line loopback, pop from acquisition fifo only when there is space in
426 // the tx_fifo. We are also allowed to pop even if there is no space if th acq entry
427 // is not data payload.
428 1/1 assign acq_fifo_rready = (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) |
Tests: T1 T2 T3
429 (target_loopback & (tx_fifo_wready | (acq_type != AcqData)));
430
431 // sync the incoming SCL and SDA signals
432 prim_flop_2sync #(
433 .Width(1),
434 .ResetValue(1'b1)
435 ) u_i2c_sync_scl (
436 .clk_i,
437 .rst_ni,
438 .d_i (scl_i),
439 .q_o (scl_sync)
440 );
441
442 prim_flop_2sync #(
443 .Width(1),
444 .ResetValue(1'b1)
445 ) u_i2c_sync_sda (
446 .clk_i,
447 .rst_ni,
448 .d_i (sda_i),
449 .q_o (sda_sync)
450 );
451
452 // Various bus collision events are detected while SCL is high.
453 logic sda_fsm, sda_fsm_q;
454 logic scl_fsm, scl_fsm_q;
455 1/1 assign sda_fsm = sda_out_controller_fsm & sda_out_target_fsm;
Tests: T1 T2 T3
456 1/1 assign scl_fsm = scl_out_controller_fsm & scl_out_target_fsm;
Tests: T1 T2 T3
457
458 always_ff @(posedge clk_i or negedge rst_ni) begin
459 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
460 1/1 sda_fsm_q <= 1'b1;
Tests: T1 T2 T3
461 1/1 scl_fsm_q <= 1'b1;
Tests: T1 T2 T3
462 end else begin
463 1/1 sda_fsm_q <= sda_fsm;
Tests: T1 T2 T3
464 1/1 scl_fsm_q <= scl_fsm;
Tests: T1 T2 T3
465 end
466 end
467
468 always_ff @(posedge clk_i or negedge rst_ni) begin
469 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
470 1/1 bus_event_detect_cnt <= '1;
Tests: T1 T2 T3
471 1/1 end else if ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q)) begin
Tests: T1 T2 T3
472 // Wait for the round-trip time on SCL changes or on SDA changes. The
473 // latter handles Start and Stop conditions, so changes while SCL is high
474 // are allowed to propagate. The rise time is used here because it
475 // should be the longer value. The (-1) term here is to account for the
476 // delay in the counter.
477 // Note that there are limits to this method of detecting arbitration.
478 // A separate, buggy device that drives clock low faster than the counter
479 // can expire would not trigger loss of arbitration.
480 1/1 bus_event_detect_cnt <= reg2hw.timing1.t_r.q + 10'(RoundTripCycles - 1);
Tests: T2 T3 T4
481 1/1 end else if (bus_event_detect_cnt != '0) begin
Tests: T1 T2 T3
482 1/1 bus_event_detect_cnt <= bus_event_detect_cnt - 1'b1;
Tests: T1 T2 T3
483 end
MISSING_ELSE
484 end
485 1/1 assign bus_event_detect = (bus_event_detect_cnt == '0);
Tests: T1 T2 T3
486 1/1 assign sda_released_but_low = bus_event_detect && scl_sync && (sda_fsm_q != sda_sync);
Tests: T1 T2 T3
487 // What about unexpected start / stop on the bits that are read?
488 1/1 assign controller_sda_interference = controller_transmitting && sda_released_but_low;
Tests: T1 T2 T3
489 1/1 assign target_arbitration_lost = target_transmitting && sda_released_but_low;
Tests: T1 T2 T3
490
491 1/1 assign event_sda_interference = controller_sda_interference;
Tests: T1 T2 T3
492
493 // The bus monitor detects starts, stops, and bus timeouts. It also reports
494 // when the bus is free for the controller to transmit.
495 i2c_bus_monitor u_i2c_bus_monitor (
496 .clk_i,
497 .rst_ni,
498
499 .scl_i (scl_sync),
500 .sda_i (sda_sync),
501
502 .controller_enable_i (host_enable),
503 .multi_controller_enable_i (reg2hw.ctrl.multi_controller_monitor_en.q),
504 .target_enable_i (target_enable),
505 .target_idle_i (target_idle),
506 .thd_dat_i (thd_dat),
507 .t_buf_i (t_buf),
508 .bus_active_timeout_i (bus_active_timeout),
509 .bus_active_timeout_en_i (bus_timeout_enable),
510 .bus_inactive_timeout_i (host_timeout),
511
512 .bus_free_o (bus_free),
513 .start_detect_o (start_detect),
514 .stop_detect_o (stop_detect),
515
516 .event_bus_active_timeout_o (event_bus_active_timeout),
517 .event_host_timeout_o (event_host_timeout)
518 );
519
520 i2c_controller_fsm #(
521 .FifoDepth(FifoDepth)
522 ) u_i2c_controller_fsm (
523 .clk_i,
524 .rst_ni,
525
526 .scl_i (scl_sync),
527 .scl_o (scl_out_controller_fsm),
528 .sda_i (sda_sync),
529 .sda_o (sda_out_controller_fsm),
530 .bus_free_i (bus_free),
531 .transmitting_o (controller_transmitting),
532
533 .host_enable_i (host_enable),
534 .halt_controller_i (status_controller_halt),
535
536 .fmt_fifo_rvalid_i (fmt_fifo_rvalid),
537 .fmt_fifo_depth_i (fmt_fifo_depth),
538 .fmt_fifo_rready_o (fmt_fifo_rready),
539
540 .fmt_byte_i (fmt_byte),
541 .fmt_flag_start_before_i (fmt_flag_start_before),
542 .fmt_flag_stop_after_i (fmt_flag_stop_after),
543 .fmt_flag_read_bytes_i (fmt_flag_read_bytes),
544 .fmt_flag_read_continue_i (fmt_flag_read_continue),
545 .fmt_flag_nak_ok_i (fmt_flag_nak_ok),
546 .unhandled_unexp_nak_i (unhandled_unexp_nak),
547 .unhandled_nak_timeout_i (reg2hw.controller_events.unhandled_nack_timeout.q),
548
549 .rx_fifo_wvalid_o (rx_fifo_wvalid),
550 .rx_fifo_wdata_o (rx_fifo_wdata),
551
552 .host_idle_o (host_idle),
553
554 .thigh_i (thigh),
555 .tlow_i (tlow),
556 .t_r_i (t_r),
557 .t_f_i (t_f),
558 .thd_sta_i (thd_sta),
559 .tsu_sta_i (tsu_sta),
560 .tsu_sto_i (tsu_sto),
561 .thd_dat_i (thd_dat),
562 .sda_interference_i (controller_sda_interference),
563 .stretch_timeout_i (bus_active_timeout),
564 .timeout_enable_i (stretch_timeout_enable),
565 .host_nack_handler_timeout_i (host_nack_handler_timeout),
566 .host_nack_handler_timeout_en_i (host_nack_handler_timeout_en),
567 .event_nak_o (event_nak),
568 .event_unhandled_nak_timeout_o (event_unhandled_nak_timeout),
569 .event_arbitration_lost_o (event_controller_arbitration_lost),
570 .event_scl_interference_o (event_scl_interference),
571 .event_stretch_timeout_o (event_stretch_timeout),
572 .event_sda_unstable_o (event_sda_unstable),
573 .event_cmd_complete_o (event_controller_cmd_complete)
574 );
575
576 i2c_target_fsm #(
577 .AcqFifoDepth(AcqFifoDepth)
578 ) u_i2c_target_fsm (
579 .clk_i,
580 .rst_ni,
581
582 .scl_i (scl_sync),
583 .scl_o (scl_out_target_fsm),
584 .sda_i (sda_sync),
585 .sda_o (sda_out_target_fsm),
586 .start_detect_i (start_detect),
587 .stop_detect_i (stop_detect),
588 .transmitting_o (target_transmitting),
589
590 .target_enable_i (target_enable),
591
592 .tx_fifo_rvalid_i (tx_fifo_rvalid),
593 .tx_fifo_rready_o (tx_fifo_rready),
594 .tx_fifo_rdata_i (tx_fifo_rdata),
595
596 .acq_fifo_wvalid_o (acq_fifo_wvalid),
597 .acq_fifo_wdata_o (acq_fifo_wdata),
598 .acq_fifo_rdata_i (acq_fifo_rdata),
599 .acq_fifo_full_o (acq_fifo_full),
600 .acq_fifo_depth_i (acq_fifo_depth),
601
602 .target_idle_o (target_idle),
603
604 .t_r_i (t_r),
605 .tsu_dat_i (tsu_dat),
606 .thd_dat_i (thd_dat),
607 .nack_timeout_i (nack_timeout),
608 .nack_timeout_en_i (nack_timeout_en),
609 .nack_addr_after_timeout_i (reg2hw.ctrl.nack_addr_after_timeout.q),
610 .arbitration_lost_i (target_arbitration_lost),
611 .bus_timeout_i (event_bus_active_timeout),
612 .unhandled_tx_stretch_event_i (unhandled_tx_stretch_event),
613 .ack_ctrl_mode_i (reg2hw.ctrl.ack_ctrl_en.q),
614 .auto_ack_cnt_o (hw2reg.target_ack_ctrl.nbytes.d),
615 .auto_ack_load_i (reg2hw.target_ack_ctrl.nbytes.qe),
616 .auto_ack_load_value_i (reg2hw.target_ack_ctrl.nbytes.q),
617 .sw_nack_i (target_ack_ctrl_sw_nack),
618 .ack_ctrl_stretching_o (target_ack_ctrl_stretching),
619 .acq_fifo_next_data_o (hw2reg.acq_fifo_next_data.d),
620 .target_address0_i (target_address0),
621 .target_mask0_i (target_mask0),
622 .target_address1_i (target_address1),
623 .target_mask1_i (target_mask1),
624 .event_target_nack_o (event_target_nack),
625 .event_read_cmd_received_o (event_read_cmd_received),
626 .event_cmd_complete_o (event_target_cmd_complete),
627 .event_tx_stretch_o (event_tx_stretch),
628 .event_unexp_stop_o (event_unexp_stop),
629 .event_tx_arbitration_lost_o (event_tx_arbitration_lost),
630 .event_tx_bus_timeout_o (event_tx_bus_timeout)
631 );
632
633 prim_intr_hw #(
634 .Width(1),
635 .IntrT("Status")
636 ) intr_hw_fmt_threshold (
637 .clk_i,
638 .rst_ni,
639 .event_intr_i (fmt_lt_threshold),
640 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fmt_threshold.q),
641 .reg2hw_intr_test_q_i (reg2hw.intr_test.fmt_threshold.q),
642 .reg2hw_intr_test_qe_i (reg2hw.intr_test.fmt_threshold.qe),
643 .reg2hw_intr_state_q_i (reg2hw.intr_state.fmt_threshold.q),
644 .hw2reg_intr_state_de_o (hw2reg.intr_state.fmt_threshold.de),
645 .hw2reg_intr_state_d_o (hw2reg.intr_state.fmt_threshold.d),
646 .intr_o (intr_fmt_threshold_o)
647 );
648
649 prim_intr_hw #(
650 .Width(1),
651 .IntrT("Status")
652 ) intr_hw_rx_threshold (
653 .clk_i,
654 .rst_ni,
655 .event_intr_i (rx_gt_threshold),
656 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_threshold.q),
657 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_threshold.q),
658 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_threshold.qe),
659 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_threshold.q),
660 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_threshold.de),
661 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_threshold.d),
662 .intr_o (intr_rx_threshold_o)
663 );
664
665 prim_intr_hw #(
666 .Width(1),
667 .IntrT("Status")
668 ) intr_hw_acq_threshold (
669 .clk_i,
670 .rst_ni,
671 .event_intr_i (acq_gt_threshold),
672 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.acq_threshold.q),
673 .reg2hw_intr_test_q_i (reg2hw.intr_test.acq_threshold.q),
674 .reg2hw_intr_test_qe_i (reg2hw.intr_test.acq_threshold.qe),
675 .reg2hw_intr_state_q_i (reg2hw.intr_state.acq_threshold.q),
676 .hw2reg_intr_state_de_o (hw2reg.intr_state.acq_threshold.de),
677 .hw2reg_intr_state_d_o (hw2reg.intr_state.acq_threshold.d),
678 .intr_o (intr_acq_threshold_o)
679 );
680
681 prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
682 .clk_i,
683 .rst_ni,
684 .event_intr_i (event_rx_overflow),
685 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
686 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_overflow.q),
687 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_overflow.qe),
688 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_overflow.q),
689 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
690 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_overflow.d),
691 .intr_o (intr_rx_overflow_o)
692 );
693
694 prim_intr_hw #(
695 .Width(1),
696 .IntrT("Status")
697 ) intr_hw_controller_halt (
698 .clk_i,
699 .rst_ni,
700 .event_intr_i (status_controller_halt),
701 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.controller_halt.q),
702 .reg2hw_intr_test_q_i (reg2hw.intr_test.controller_halt.q),
703 .reg2hw_intr_test_qe_i (reg2hw.intr_test.controller_halt.qe),
704 .reg2hw_intr_state_q_i (reg2hw.intr_state.controller_halt.q),
705 .hw2reg_intr_state_de_o (hw2reg.intr_state.controller_halt.de),
706 .hw2reg_intr_state_d_o (hw2reg.intr_state.controller_halt.d),
707 .intr_o (intr_controller_halt_o)
708 );
709
710 prim_intr_hw #(.Width(1)) intr_hw_scl_interference (
711 .clk_i,
712 .rst_ni,
713 .event_intr_i (event_scl_interference),
714 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.scl_interference.q),
715 .reg2hw_intr_test_q_i (reg2hw.intr_test.scl_interference.q),
716 .reg2hw_intr_test_qe_i (reg2hw.intr_test.scl_interference.qe),
717 .reg2hw_intr_state_q_i (reg2hw.intr_state.scl_interference.q),
718 .hw2reg_intr_state_de_o (hw2reg.intr_state.scl_interference.de),
719 .hw2reg_intr_state_d_o (hw2reg.intr_state.scl_interference.d),
720 .intr_o (intr_scl_interference_o)
721 );
722
723 prim_intr_hw #(.Width(1)) intr_hw_sda_interference (
724 .clk_i,
725 .rst_ni,
726 .event_intr_i (event_sda_interference),
727 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.sda_interference.q),
728 .reg2hw_intr_test_q_i (reg2hw.intr_test.sda_interference.q),
729 .reg2hw_intr_test_qe_i (reg2hw.intr_test.sda_interference.qe),
730 .reg2hw_intr_state_q_i (reg2hw.intr_state.sda_interference.q),
731 .hw2reg_intr_state_de_o (hw2reg.intr_state.sda_interference.de),
732 .hw2reg_intr_state_d_o (hw2reg.intr_state.sda_interference.d),
733 .intr_o (intr_sda_interference_o)
734 );
735
736 prim_intr_hw #(.Width(1)) intr_hw_stretch_timeout (
737 .clk_i,
738 .rst_ni,
739 .event_intr_i (event_stretch_timeout),
740 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.stretch_timeout.q),
741 .reg2hw_intr_test_q_i (reg2hw.intr_test.stretch_timeout.q),
742 .reg2hw_intr_test_qe_i (reg2hw.intr_test.stretch_timeout.qe),
743 .reg2hw_intr_state_q_i (reg2hw.intr_state.stretch_timeout.q),
744 .hw2reg_intr_state_de_o (hw2reg.intr_state.stretch_timeout.de),
745 .hw2reg_intr_state_d_o (hw2reg.intr_state.stretch_timeout.d),
746 .intr_o (intr_stretch_timeout_o)
747 );
748
749 prim_intr_hw #(.Width(1)) intr_hw_sda_unstable (
750 .clk_i,
751 .rst_ni,
752 .event_intr_i (event_sda_unstable),
753 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.sda_unstable.q),
754 .reg2hw_intr_test_q_i (reg2hw.intr_test.sda_unstable.q),
755 .reg2hw_intr_test_qe_i (reg2hw.intr_test.sda_unstable.qe),
756 .reg2hw_intr_state_q_i (reg2hw.intr_state.sda_unstable.q),
757 .hw2reg_intr_state_de_o (hw2reg.intr_state.sda_unstable.de),
758 .hw2reg_intr_state_d_o (hw2reg.intr_state.sda_unstable.d),
759 .intr_o (intr_sda_unstable_o)
760 );
761
762 prim_intr_hw #(.Width(1)) intr_hw_cmd_complete (
763 .clk_i,
764 .rst_ni,
765 .event_intr_i (event_cmd_complete),
766 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.cmd_complete.q),
767 .reg2hw_intr_test_q_i (reg2hw.intr_test.cmd_complete.q),
768 .reg2hw_intr_test_qe_i (reg2hw.intr_test.cmd_complete.qe),
769 .reg2hw_intr_state_q_i (reg2hw.intr_state.cmd_complete.q),
770 .hw2reg_intr_state_de_o (hw2reg.intr_state.cmd_complete.de),
771 .hw2reg_intr_state_d_o (hw2reg.intr_state.cmd_complete.d),
772 .intr_o (intr_cmd_complete_o)
773 );
774
775 prim_intr_hw #(
776 .Width(1),
777 .IntrT("Status")
778 ) intr_hw_tx_stretch (
779 .clk_i,
780 .rst_ni,
781 .event_intr_i (event_tx_stretch),
782 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_stretch.q),
783 .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_stretch.q),
784 .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_stretch.qe),
785 .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_stretch.q),
786 .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_stretch.de),
787 .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_stretch.d),
788 .intr_o (intr_tx_stretch_o)
789 );
790
791 prim_intr_hw #(
792 .Width(1),
793 .IntrT("Status")
794 ) intr_hw_tx_threshold (
795 .clk_i,
796 .rst_ni,
797 .event_intr_i (tx_lt_threshold),
798 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_threshold.q),
799 .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_threshold.q),
800 .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_threshold.qe),
801 .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_threshold.q),
802 .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_threshold.de),
803 .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_threshold.d),
804 .intr_o (intr_tx_threshold_o)
805 );
806
807 prim_intr_hw #(
808 .Width(1),
809 .IntrT("Status")
810 ) intr_hw_acq_overflow (
811 .clk_i,
812 .rst_ni,
813 .event_intr_i (event_acq_stretch),
814 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.acq_stretch.q),
815 .reg2hw_intr_test_q_i (reg2hw.intr_test.acq_stretch.q),
816 .reg2hw_intr_test_qe_i (reg2hw.intr_test.acq_stretch.qe),
817 .reg2hw_intr_state_q_i (reg2hw.intr_state.acq_stretch.q),
818 .hw2reg_intr_state_de_o (hw2reg.intr_state.acq_stretch.de),
819 .hw2reg_intr_state_d_o (hw2reg.intr_state.acq_stretch.d),
820 .intr_o (intr_acq_stretch_o)
821 );
822
823 prim_intr_hw #(.Width(1)) intr_hw_unexp_stop (
824 .clk_i,
825 .rst_ni,
826 .event_intr_i (event_unexp_stop),
827 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.unexp_stop.q),
828 .reg2hw_intr_test_q_i (reg2hw.intr_test.unexp_stop.q),
829 .reg2hw_intr_test_qe_i (reg2hw.intr_test.unexp_stop.qe),
830 .reg2hw_intr_state_q_i (reg2hw.intr_state.unexp_stop.q),
831 .hw2reg_intr_state_de_o (hw2reg.intr_state.unexp_stop.de),
832 .hw2reg_intr_state_d_o (hw2reg.intr_state.unexp_stop.d),
833 .intr_o (intr_unexp_stop_o)
834 );
835
836 prim_intr_hw #(.Width(1)) intr_hw_host_timeout (
837 .clk_i,
838 .rst_ni,
839 .event_intr_i (event_host_timeout),
840 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.host_timeout.q),
841 .reg2hw_intr_test_q_i (reg2hw.intr_test.host_timeout.q),
842 .reg2hw_intr_test_qe_i (reg2hw.intr_test.host_timeout.qe),
843 .reg2hw_intr_state_q_i (reg2hw.intr_state.host_timeout.q),
844 .hw2reg_intr_state_de_o (hw2reg.intr_state.host_timeout.de),
845 .hw2reg_intr_state_d_o (hw2reg.intr_state.host_timeout.d),
846 .intr_o (intr_host_timeout_o)
847 );
848
849 assign hw2reg.controller_events.nack.d = 1'b1;
850 1/1 assign hw2reg.controller_events.nack.de = event_nak;
Tests: T1 T2 T3
851 assign hw2reg.controller_events.unhandled_nack_timeout.d = 1'b1;
852 1/1 assign hw2reg.controller_events.unhandled_nack_timeout.de = event_unhandled_nak_timeout;
Tests: T1 T2 T3
853 assign hw2reg.controller_events.bus_timeout.d = 1'b1;
854 1/1 assign hw2reg.controller_events.bus_timeout.de = event_bus_active_timeout && !host_idle;
Tests: T1 T2 T3
855 assign hw2reg.controller_events.arbitration_lost.d = 1'b1;
856 1/1 assign hw2reg.controller_events.arbitration_lost.de = event_controller_arbitration_lost;
Tests: T1 T2 T3
857 1/1 assign status_controller_halt = | {
Tests: T1 T2 T3
858 reg2hw.controller_events.nack.q,
859 reg2hw.controller_events.unhandled_nack_timeout.q,
860 reg2hw.controller_events.bus_timeout.q,
861 reg2hw.controller_events.arbitration_lost.q
862 };
863
864 assign hw2reg.target_events.tx_pending.d = 1'b1;
865 1/1 assign hw2reg.target_events.tx_pending.de = event_read_cmd_received &&
Tests: T1 T2 T3
866 reg2hw.ctrl.tx_stretch_ctrl_en.q;
867 assign hw2reg.target_events.bus_timeout.d = 1'b1;
868 1/1 assign hw2reg.target_events.bus_timeout.de = event_tx_bus_timeout;
Tests: T1 T2 T3
869 assign hw2reg.target_events.arbitration_lost.d = 1'b1;
870 1/1 assign hw2reg.target_events.arbitration_lost.de = event_tx_arbitration_lost;
Tests: T1 T2 T3
871 1/1 assign unhandled_tx_stretch_event = | {
Tests: T1 T2 T3
Cond Coverage for Module :
i2c_core
| Total | Covered | Percent |
|---|
| Conditions | 130 | 103 | 79.23 |
| Logical | 130 | 103 | 79.23 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 237
EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T63,T64,T60 |
LINE 242
EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T102,T80 |
LINE 243
EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T102,T80 |
LINE 249
EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
--------------1-------------- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T44,T45 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 253
EXPRESSION (target_enable & line_loopback)
------1------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Not Covered | |
LINE 267
EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
-----------1---------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T10,T45,T46 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 268
EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
-----------1---------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 294
EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
------------1----------- -------------------------2------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 294
SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 296
EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
------------1----------- -----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Not Covered | |
LINE 296
SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 303
EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
---------------1-------------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T46,T47,T48 |
| 1 | 1 | Not Covered | |
LINE 306
EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
------------1----------- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T10,T46 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 307
EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
------------1------------ -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T10,T46 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 311
EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
------------1----------- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T10,T46 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 312
EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
------------1------------ -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T10,T47 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 325
EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
-------1------ ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T6,T7 |
| 1 | 1 | Covered | T6,T35,T103 |
LINE 326
EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
------1------ -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T46,T47,T48 |
| 1 | 0 | Covered | T10,T52,T63 |
LINE 331
EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
----------1---------- ----------2---------- ----------3--------- ----------4---------- ----------5---------- ----------6----------
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | 1 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | 1 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 344
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 345
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 346
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 347
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 348
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 349
EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 419
EXPRESSION (target_enable & (acq_type == AcqData))
------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Covered | T10,T44,T45 |
LINE 419
SUB-EXPRESSION (acq_type == AcqData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 422
EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 422
SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 423
EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 428
EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
--------------------------1------------------------- ------------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T10,T44,T45 |
LINE 428
SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
-----------1----------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T10,T44,T45 |
LINE 428
SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
-------1------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 428
SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T60,T61,T62 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 428
SUB-EXPRESSION (acq_type != AcqData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T44,T45 |
LINE 455
EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
-----------1---------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 456
EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
-----------1---------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T10,T45,T46 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 471
EXPRESSION ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q))
-----------1---------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T2,T3,T4 |
LINE 471
SUB-EXPRESSION (scl_fsm != scl_fsm_q)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 471
SUB-EXPRESSION (sda_fsm != sda_fsm_q)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 481
EXPRESSION (bus_event_detect_cnt != '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 485
EXPRESSION (bus_event_detect_cnt == '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 486
EXPRESSION (bus_event_detect && scl_sync && (sda_fsm_q != sda_sync))
--------1------- ----2--- -----------3-----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 486
SUB-EXPRESSION (sda_fsm_q != sda_sync)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 488
EXPRESSION (controller_transmitting && sda_released_but_low)
-----------1----------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T8,T17,T18 |
LINE 489
EXPRESSION (target_transmitting && sda_released_but_low)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Not Covered | |
LINE 854
EXPRESSION (event_bus_active_timeout && ((!host_idle)))
------------1----------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 865
EXPRESSION (event_read_cmd_received && reg2hw.ctrl.tx_stretch_ctrl_en.q)
-----------1----------- ----------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T70,T60,T71 |
| 1 | 0 | Covered | T10,T44,T45 |
| 1 | 1 | Covered | T70,T60,T71 |
Branch Coverage for Module :
i2c_core
| Line No. | Total | Covered | Percent |
| Branches |
|
30 |
28 |
93.33 |
| TERNARY |
242 |
2 |
2 |
100.00 |
| TERNARY |
243 |
2 |
2 |
100.00 |
| TERNARY |
344 |
2 |
2 |
100.00 |
| TERNARY |
345 |
2 |
2 |
100.00 |
| TERNARY |
346 |
2 |
2 |
100.00 |
| TERNARY |
347 |
2 |
2 |
100.00 |
| TERNARY |
348 |
2 |
2 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| TERNARY |
422 |
2 |
1 |
50.00 |
| TERNARY |
423 |
2 |
1 |
50.00 |
| IF |
262 |
2 |
2 |
100.00 |
| IF |
274 |
2 |
2 |
100.00 |
| IF |
459 |
2 |
2 |
100.00 |
| IF |
469 |
4 |
4 |
100.00 |
242 assign scl_o = override ? reg2hw.ovrd.sclval : scl_out_fsm;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T102,T80 |
| 0 |
Covered |
T1,T2,T3 |
243 assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T102,T80 |
| 0 |
Covered |
T1,T2,T3 |
344 assign fmt_byte = fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
345 assign fmt_flag_start_before = fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
346 assign fmt_flag_stop_after = fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
347 assign fmt_flag_read_bytes = fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
348 assign fmt_flag_read_continue = fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
349 assign fmt_flag_nak_ok = fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
422 assign tx_fifo_wvalid = target_loopback ? acq_fifo_rvalid & valid_target_lb_wr : reg2hw.txdata.qe;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
423 assign tx_fifo_wdata = target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
262 if (!rst_ni) begin
-1-
263 scl_out_fsm <= 1'b1;
==>
264 sda_out_fsm <= 1'b1;
265 end else begin
266 // Drive 0 if any FSM requests it.
267 scl_out_fsm <= scl_out_controller_fsm & scl_out_target_fsm;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
274 if(!rst_ni) begin
-1-
275 scl_rx_val <= 16'h0;
==>
276 sda_rx_val <= 16'h0;
277 end else begin
278 scl_rx_val <= {scl_rx_val[14:0], scl_i};
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
459 if (!rst_ni) begin
-1-
460 sda_fsm_q <= 1'b1;
==>
461 scl_fsm_q <= 1'b1;
462 end else begin
463 sda_fsm_q <= sda_fsm;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
469 if (!rst_ni) begin
-1-
470 bus_event_detect_cnt <= '1;
==>
471 end else if ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q)) begin
-2-
472 // Wait for the round-trip time on SCL changes or on SDA changes. The
473 // latter handles Start and Stop conditions, so changes while SCL is high
474 // are allowed to propagate. The rise time is used here because it
475 // should be the longer value. The (-1) term here is to account for the
476 // delay in the counter.
477 // Note that there are limits to this method of detecting arbitration.
478 // A separate, buggy device that drives clock low faster than the counter
479 // can expire would not trigger loss of arbitration.
480 bus_event_detect_cnt <= reg2hw.timing1.t_r.q + 10'(RoundTripCycles - 1);
==>
481 end else if (bus_event_detect_cnt != '0) begin
-3-
482 bus_event_detect_cnt <= bus_event_detect_cnt - 1'b1;
==>
483 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T3,T4 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T2,T3,T4 |
Assert Coverage for Module :
i2c_core
Assertion Details
AcqFifoDepthValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683 |
1683 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
FifoDepthValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1683 |
1683 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |