Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.48 100.00 100.00 93.91 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 100.00 100.00 93.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.44 97.23 89.50 97.22 72.02 94.23 98.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 87.75 96.26 83.88 72.02 91.56 95.04
i2c_csr_assert 93.75 93.75
tlul_assert_device 100.00 100.00
u_reg 98.65 98.59 97.07 100.00 97.58 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00


68                      
69         1/1            assign alert_test = {
           Tests:       T1 T2 T3 
70                          reg2hw.alert_test.q &
71                          reg2hw.alert_test.qe
72                        };
73                      
74                        for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
75                          prim_alert_sender #(
76                            .AsyncOn(AlertAsyncOn[i]),
77                            .IsFatal(1'b1)
78                          ) u_prim_alert_sender (
79                            .clk_i,
80                            .rst_ni,
81                            .alert_test_i  ( alert_test[i] ),
82                            .alert_req_i   ( alerts[0]     ),
83                            .alert_ack_o   (               ),
84                            .alert_state_o (               ),
85                            .alert_rx_i    ( alert_rx_i[i] ),
86                            .alert_tx_o    ( alert_tx_o[i] )
87                          );
88                        end
89                      
90                        logic scl_int;
91                        logic sda_int;
92                      
93                        i2c_core #(
94                          .InputDelayCycles(InputDelayCycles)
95                        ) i2c_core (
96                          .clk_i,
97                          .rst_ni,
98                          .ram_cfg_i,
99                      
100                         .reg2hw,
101                         .hw2reg,
102                     
103                         .scl_i(cio_scl_i),
104                         .scl_o(scl_int),
105                         .sda_i(cio_sda_i),
106                         .sda_o(sda_int),
107                     
108                         .intr_fmt_threshold_o,
109                         .intr_rx_threshold_o,
110                         .intr_acq_threshold_o,
111                         .intr_rx_overflow_o,
112                         .intr_controller_halt_o,
113                         .intr_scl_interference_o,
114                         .intr_sda_interference_o,
115                         .intr_stretch_timeout_o,
116                         .intr_sda_unstable_o,
117                         .intr_cmd_complete_o,
118                         .intr_tx_stretch_o,
119                         .intr_tx_threshold_o,
120                         .intr_acq_stretch_o,
121                         .intr_unexp_stop_o,
122                         .intr_host_timeout_o
123                       );
124                     
125                       // For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
126                       // Asserting scl or sda high should be equivalent to a tri-state output.
127                       // The output, when enabled, should only assert low.
128                     
129                       assign cio_scl_o = 1'b0;
130                       assign cio_sda_o = 1'b0;
131                     
132        1/1            assign cio_scl_en_o = ~scl_int;
           Tests:       T1 T2 T3 
133        1/1            assign cio_sda_en_o = ~sda_int;
           Tests:       T1 T2 T3 
Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       69
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT99,T100,T101
10CoveredT1,T2,T3
11CoveredT99,T100,T101
Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 51 45 88.24
Total Bits 394 370 93.91
Total Bits 0->1 197 185 93.91
Total Bits 1->0 197 185 93.91

Ports 51 45 88.24
Port Bits 394 370 93.91
Port Bits 0->1 197 185 93.91
Port Bits 1->0 197 185 93.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T8,T182,T17 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T19,T45 Yes T1,T19,T45 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T183,T184,T185 Yes T183,T184,T185 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T99,T182,T100 Yes T99,T182,T100 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T99,T182,T100 Yes T99,T182,T100 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T2,T4,T5 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T2,T4,T5 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T4,T5,T7 Yes T2,T4,T5 OUTPUT
intr_rx_threshold_o Yes Yes T6,T43,T24 Yes T6,T43,T24 OUTPUT
intr_acq_threshold_o Yes Yes T10,T74,T52 Yes T10,T74,T52 OUTPUT
intr_rx_overflow_o Yes Yes T6,T35,T103 Yes T6,T35,T103 OUTPUT
intr_controller_halt_o Yes Yes T8,T11,T17 Yes T8,T11,T17 OUTPUT
intr_scl_interference_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_sda_interference_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_stretch_timeout_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
intr_sda_unstable_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
intr_cmd_complete_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
intr_tx_stretch_o Yes Yes T10,T45,T46 Yes T10,T45,T46 OUTPUT
intr_tx_threshold_o Yes Yes T8,T74,T48 Yes T2,T4,T5 OUTPUT
intr_acq_stretch_o Yes Yes T10,T46,T47 Yes T10,T46,T47 OUTPUT
intr_unexp_stop_o Yes Yes T10,T53,T180 Yes T10,T53,T180 OUTPUT
intr_host_timeout_o Yes Yes T72,T75,T76 Yes T72,T75,T76 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 384075267 383907368 0 0
CioSclEnKnownO_A 384075267 383907368 0 0
CioSclKnownO_A 384075267 383907368 0 0
CioSdaEnKnownO_A 384075267 383907368 0 0
CioSdaKnownO_A 384075267 383907368 0 0
FpvSecCmRegWeOnehotCheck_A 384075267 60 0 0
IntrAcqStretchKnownO_A 384075267 383907368 0 0
IntrAcqWtmkKnownO_A 384075267 383907368 0 0
IntrCommandCompleteKnownO_A 384075267 383907368 0 0
IntrControllerHaltKnownO_A 384075267 383907368 0 0
IntrFmtWtmkKnownO_A 384075267 383907368 0 0
IntrHostTimeoutKnownO_A 384075267 383907368 0 0
IntrRxOflwKnownO_A 384075267 383907368 0 0
IntrRxWtmkKnownO_A 384075267 383907368 0 0
IntrSclInterfKnownO_A 384075267 383907368 0 0
IntrSdaInterfKnownO_A 384075267 383907368 0 0
IntrSdaUnstableKnownO_A 384075267 383907368 0 0
IntrStretchTimeoutKnownO_A 384075267 383907368 0 0
IntrTxStretchKnownO_A 384075267 383907368 0 0
IntrTxWtmkKnownO_A 384075267 383907368 0 0
IntrUnexpStopKnownO_A 384075267 383907368 0 0
TlAReadyKnownO_A 384075267 383907368 0 0
TlDValidKnownO_A 384075267 383907368 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 60 0 0
T11 42128 0 0 0
T38 10459 0 0 0
T60 15840 0 0 0
T80 2638 0 0 0
T102 1218 0 0 0
T154 20473 0 0 0
T161 382490 0 0 0
T169 20516 0 0 0
T170 155438 0 0 0
T182 5655 20 0 0
T186 0 10 0 0
T187 0 10 0 0
T188 0 10 0 0
T189 0 10 0 0

IntrAcqStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384075267 383907368 0 0
T1 931 866 0 0
T2 130133 130059 0 0
T3 9154 9102 0 0
T4 20775 20688 0 0
T5 47724 47644 0 0
T6 153117 153053 0 0
T7 8045 7991 0 0
T8 11927 11210 0 0
T9 44843 44754 0 0
T10 219025 218958 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%