Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	384694279	0	0	0
ctrl_rd_A	384694279	709	0	0
host_fifo_config_rd_A	384694279	3304	0	0
host_nack_handler_timeout_rd_A	384694279	461	0	0
host_timeout_ctrl_rd_A	384694279	490	0	0
intr_enable_rd_A	384694279	1410	0	0
ovrd_rd_A	384694279	951	0	0
target_fifo_config_rd_A	384694279	571	0	0
target_id_rd_A	384694279	630	0	0
target_timeout_ctrl_rd_A	384694279	563	0	0
timeout_ctrl_rd_A	384694279	666	0	0
timing0_rd_A	384694279	504	0	0
timing1_rd_A	384694279	566	0	0
timing2_rd_A	384694279	581	0	0
timing3_rd_A	384694279	478	0	0
timing4_rd_A	384694279	491	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	709	0	0
T104	2223	22	0	0
T105	6031	10	0	0
T106	2193	4	0	0
T107	11536	22	0	0
T108	1746	8	0	0
T109	9716	115	0	0
T110	2565	8	0	0
T111	14587	22	0	0
T112	6615	77	0	0
T113	2313	19	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	3304	0	0
T114	501929	210	0	0
T115	0	153	0	0
T116	0	94	0	0
T117	0	187	0	0
T118	0	240	0	0
T119	0	189	0	0
T120	0	88	0	0
T121	0	54	0	0
T122	0	194	0	0
T123	0	209	0	0
T124	51394	0	0	0
T125	26091	0	0	0
T126	47890	0	0	0
T127	336417	0	0	0
T128	8074	0	0	0
T129	58377	0	0	0
T130	56491	0	0	0
T131	6345	0	0	0
T132	48915	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	461	0	0
T105	6031	14	0	0
T106	2193	6	0	0
T107	11536	41	0	0
T108	1746	6	0	0
T109	9716	112	0	0
T110	2565	3	0	0
T111	14587	15	0	0
T112	6615	37	0	0
T113	2313	16	0	0
T133	7319	14	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	490	0	0
T105	6031	11	0	0
T106	2193	3	0	0
T107	11536	35	0	0
T108	1746	7	0	0
T109	9716	114	0	0
T110	2565	5	0	0
T111	14587	36	0	0
T112	6615	29	0	0
T133	7319	8	0	0
T134	4165	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	1410	0	0
T104	2223	62	0	0
T105	6031	4	0	0
T106	2193	5	0	0
T107	11536	46	0	0
T108	1746	6	0	0
T109	9716	140	0	0
T110	2565	7	0	0
T111	14587	20	0	0
T135	1972	14	0	0
T136	1007	9	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	951	0	0
T58	112643	0	0	0
T68	45632	0	0	0
T137	2968	32	0	0
T138	0	39	0	0
T139	0	43	0	0
T140	0	56	0	0
T141	0	51	0	0
T142	0	43	0	0
T143	0	78	0	0
T144	0	23	0	0
T145	0	29	0	0
T146	0	53	0	0
T147	8498	0	0	0
T148	12813	0	0	0
T149	192865	0	0	0
T150	35605	0	0	0
T151	118456	0	0	0
T152	10176	0	0	0
T153	23309	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	571	0	0
T104	2223	9	0	0
T105	6031	25	0	0
T106	2193	3	0	0
T107	11536	26	0	0
T108	1746	1	0	0
T109	9716	118	0	0
T110	2565	7	0	0
T111	14587	43	0	0
T112	6615	46	0	0
T113	2313	2	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	630	0	0
T104	2223	15	0	0
T105	6031	29	0	0
T106	2193	7	0	0
T107	11536	20	0	0
T108	1746	2	0	0
T109	9716	127	0	0
T110	2565	15	0	0
T111	14587	30	0	0
T112	6615	50	0	0
T113	2313	4	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	563	0	0
T104	2223	1	0	0
T105	6031	17	0	0
T106	2193	7	0	0
T107	11536	42	0	0
T108	1746	3	0	0
T109	9716	148	0	0
T110	2565	19	0	0
T111	14587	16	0	0
T112	6615	13	0	0
T133	7319	30	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	666	0	0
T104	2223	10	0	0
T105	6031	17	0	0
T106	2193	1	0	0
T107	11536	62	0	0
T108	1746	1	0	0
T109	9716	94	0	0
T110	2565	9	0	0
T111	14587	47	0	0
T112	6615	69	0	0
T133	7319	46	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	504	0	0
T105	6031	12	0	0
T107	11536	35	0	0
T108	1746	5	0	0
T109	9716	140	0	0
T110	2565	5	0	0
T111	14587	28	0	0
T112	6615	33	0	0
T113	2313	1	0	0
T133	7319	46	0	0
T134	4165	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	566	0	0
T104	2223	6	0	0
T105	6031	22	0	0
T106	2193	7	0	0
T107	11536	25	0	0
T108	1746	11	0	0
T109	9716	123	0	0
T110	2565	5	0	0
T111	14587	19	0	0
T112	6615	22	0	0
T113	2313	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	581	0	0
T104	2223	15	0	0
T105	6031	13	0	0
T106	2193	6	0	0
T107	11536	39	0	0
T108	1746	10	0	0
T109	9716	149	0	0
T110	2565	16	0	0
T111	14587	5	0	0
T112	6615	22	0	0
T133	7319	35	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	478	0	0
T104	2223	13	0	0
T105	6031	14	0	0
T106	2193	1	0	0
T107	11536	44	0	0
T108	1746	2	0	0
T109	9716	99	0	0
T110	2565	4	0	0
T111	14587	10	0	0
T112	6615	31	0	0
T113	2313	3	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384694279	491	0	0
T104	2223	1	0	0
T105	6031	2	0	0
T107	11536	33	0	0
T108	1746	6	0	0
T109	9716	113	0	0
T110	2565	3	0	0
T111	14587	17	0	0
T112	6615	44	0	0
T113	2313	4	0	0
T133	7319	44	0	0