Group : i2c_env_pkg::i2c_scl_sda_override_cg
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Group : i2c_env_pkg::i2c_scl_sda_override_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.scl_sda_override_cg 100.00 1 100 1 64 64



Group Instance : i2c_env_pkg.scl_sda_override_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance i2c_env_pkg.scl_sda_override_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_sclval 2 0 2 100.00 100 1 1 2
cp_sdaval 2 0 2 100.00 100 1 1 2
cp_txorvden 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cp_txorvden_x_sclval 4 0 4 100.00 100 1 1 0
cp_txorvden_x_sdaval 4 0 4 100.00 100 1 1 0


Summary for Variable cp_sclval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sclval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 376 1 T1 13 T97 6 T98 7
auto[1] 394 1 T1 6 T97 7 T98 12


Summary for Variable cp_sdaval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sdaval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 367 1 T1 9 T97 5 T98 12
auto[1] 403 1 T1 10 T97 8 T98 7


Summary for Variable cp_txorvden

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txorvden

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 392 1 T1 11 T97 9 T98 10
auto[1] 378 1 T1 8 T97 4 T98 9


Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins
cp_txorvden   cp_sclval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 193 1 T1 8 T97 2 T98 4
auto[0] auto[1] 199 1 T1 3 T97 7 T98 6
auto[1] auto[0] 183 1 T1 5 T97 4 T98 3
auto[1] auto[1] 195 1 T1 3 T98 6 T291 3


Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins
cp_txorvden   cp_sdaval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 196 1 T1 5 T97 4 T98 5
auto[0] auto[1] 196 1 T1 6 T97 5 T98 5
auto[1] auto[0] 171 1 T1 4 T97 1 T98 7
auto[1] auto[1] 207 1 T1 4 T97 3 T98 2