Summary for Variable RStart_before_read_data_ACK_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_before_read_data_ACK_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Start_before_read_data_ACK_Nack |
13030 |
1 |
|
|
T6 |
1 |
|
T8 |
18 |
|
T9 |
13 |
Summary for Variable RStart_during_address_Ack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_address_Ack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
Start_during_address_Acknowledge |
8 |
1 |
|
|
T52 |
4 |
|
T53 |
4 |
Summary for Variable RStart_during_address_transmission_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for RStart_during_address_transmission_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Start_during_address_transmission |
0 |
1 |
1 |
|
Summary for Variable RStart_during_read_data_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_read_data_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
Start_during_read_data |
24 |
1 |
|
|
T52 |
12 |
|
T53 |
12 |
Summary for Variable RStart_during_rw_bit_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for RStart_during_rw_bit_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Start_during_rw_bit |
0 |
1 |
1 |
|
Summary for Variable RStart_during_write_data_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_write_data_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Start_during_write_data |
22440 |
1 |
|
|
T8 |
14 |
|
T9 |
6 |
|
T10 |
10 |
Summary for Variable Read_data_ack_before_stop_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Read_data_ack_before_stop_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Read_data_ack_before_stop |
0 |
1 |
1 |
|
Summary for Variable Rstart_after_Address_Ack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Rstart_after_Address_Ack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Rstart_after_Address_Ack |
27 |
1 |
|
|
T52 |
10 |
|
T53 |
10 |
|
T258 |
1 |
Summary for Variable Rstart_after_Address_Nack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Rstart_after_Address_Nack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Rstart_after_Address_Nack |
65 |
1 |
|
|
T52 |
4 |
|
T11 |
2 |
|
T53 |
4 |
Summary for Variable Start_followed_by_Rstart_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
1 |
0 |
1 |
100.00 |
Automatically Generated Bins for Start_followed_by_Rstart_cp
Excluded/Illegal bins
| | |
unused |
0 |
Excluded |
[auto[0]] |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[1] |
3 |
1 |
|
|
T142 |
2 |
|
T259 |
1 |
Summary for Variable Stop_after_read_data_Nack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_read_data_Nack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Stop_after_read_data_Nack |
11766 |
1 |
|
|
T7 |
2 |
|
T8 |
9 |
|
T10 |
4 |
Summary for Variable Stop_after_read_data_ack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_after_read_data_ack_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Stop_after_read_data_ack |
0 |
1 |
1 |
|
Summary for Variable Stop_after_write_data_Nack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_write_data_Nack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Stop_after_write_data_Nack |
63 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T13 |
4 |
Summary for Variable Stop_after_write_data_ack_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_write_data_ack_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Stop_after_write_data_ack |
9760 |
1 |
|
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Variable Stop_without_ACK_after_addr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_without_ACK_after_addr_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Stop_without_ACK_after_addr |
0 |
1 |
1 |
|
Summary for Variable Stop_without_ACK_after_data_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_without_ACK_after_data_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Stop_without_ACK_after_data |
6482 |
1 |
|
|
T8 |
2 |
|
T10 |
7 |
|
T45 |
3 |
Summary for Variable Stop_without_ACK_after_read_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_without_ACK_after_read_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Stop_without_ACK_after_read |
0 |
1 |
1 |
|
Summary for Variable Stop_without_ACK_after_write_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_without_ACK_after_write_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
Stop_without_ACK_after_write |
0 |
1 |
1 |
|
Summary for Variable bus_state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
17 |
0 |
17 |
100.00 |
User Defined Bins for bus_state_cp
Bins
| | | | | | | | | | | | |
idle |
238480 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T3 |
1 |
stop |
22613 |
1 |
|
|
T1 |
2 |
|
T5 |
18 |
|
T7 |
5 |
write_data_nack |
28838 |
1 |
|
|
T52 |
6 |
|
T11 |
241 |
|
T63 |
4 |
write_data_ack |
1481861 |
1 |
|
|
T3 |
42 |
|
T4 |
324 |
|
T5 |
552 |
read_data_nack |
94742 |
1 |
|
|
T6 |
3 |
|
T7 |
8 |
|
T8 |
90 |
read_data_ack |
1220050 |
1 |
|
|
T6 |
20 |
|
T7 |
125 |
|
T8 |
573 |
write_data |
10198078 |
1 |
|
|
T3 |
252 |
|
T4 |
1958 |
|
T5 |
3324 |
read_data |
8546518 |
1 |
|
|
T6 |
146 |
|
T7 |
905 |
|
T8 |
3946 |
write_addr_nack |
30351 |
1 |
|
|
T52 |
4 |
|
T11 |
358 |
|
T53 |
4 |
write_addr_ack |
113216 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
59 |
read_addr_nack |
70142 |
1 |
|
|
T11 |
30 |
|
T12 |
3134 |
|
T13 |
1052 |
read_addr_ack |
89760 |
1 |
|
|
T6 |
3 |
|
T7 |
11 |
|
T8 |
94 |
write |
135646 |
1 |
|
|
T3 |
4 |
|
T4 |
4 |
|
T5 |
76 |
read |
77360 |
1 |
|
|
T6 |
3 |
|
T7 |
12 |
|
T8 |
81 |
addr |
1247412 |
1 |
|
|
T3 |
18 |
|
T4 |
17 |
|
T5 |
337 |
rstart |
92980 |
1 |
|
|
T6 |
3 |
|
T7 |
6 |
|
T8 |
81 |
start |
60789 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
47 |
Summary for Variable ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for ip_mode_cp
Bins
| | | | | | | | | | | | |
device |
13090695 |
1 |
|
|
T6 |
460 |
|
T8 |
8758 |
|
T9 |
2178 |
host |
10658141 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T3 |
322 |
Summary for Variable num_rd_bytes_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for num_rd_bytes_cp
Bins
| | | | | | | | | | | | |
sixtyfour |
37484 |
1 |
|
|
T26 |
58 |
|
T190 |
24 |
|
T78 |
4 |
high |
1346297 |
1 |
|
|
T71 |
53 |
|
T72 |
26 |
|
T26 |
1414 |
mid |
2089787 |
1 |
|
|
T8 |
180 |
|
T10 |
229 |
|
T44 |
176 |
low |
4863504 |
1 |
|
|
T6 |
124 |
|
T7 |
934 |
|
T8 |
3405 |
one |
529238 |
1 |
|
|
T6 |
24 |
|
T7 |
56 |
|
T8 |
467 |
Summary for Variable num_wr_bytes_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for num_wr_bytes_cp
Bins
| | | | | | | | | | | | |
sixtyfour |
40371 |
1 |
|
|
T4 |
24 |
|
T52 |
114 |
|
T63 |
28 |
high |
1286967 |
1 |
|
|
T4 |
476 |
|
T10 |
441 |
|
T52 |
2350 |
mid |
2030754 |
1 |
|
|
T4 |
544 |
|
T5 |
751 |
|
T7 |
254 |
low |
5409340 |
1 |
|
|
T3 |
249 |
|
T4 |
476 |
|
T5 |
2395 |
one |
667921 |
1 |
|
|
T3 |
24 |
|
T4 |
24 |
|
T5 |
333 |
Summary for Cross bus_state_x_ip_mode_cp
Samples crossed: bus_state_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
34 |
1 |
33 |
97.06 |
1 |
Automatically Generated Cross Bins for bus_state_x_ip_mode_cp
Uncovered bins
bus_state_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[read_addr_nack] |
[device] |
0 |
1 |
1 |
|
Covered bins
| | | | | | | | | | | | | |
idle |
device |
235921 |
1 |
|
|
T6 |
1 |
|
T8 |
1 |
|
T9 |
1 |
idle |
host |
2559 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T3 |
1 |
stop |
device |
12832 |
1 |
|
|
T8 |
11 |
|
T10 |
11 |
|
T45 |
4 |
stop |
host |
9781 |
1 |
|
|
T1 |
2 |
|
T5 |
18 |
|
T7 |
5 |
write_data_nack |
device |
388 |
1 |
|
|
T52 |
6 |
|
T63 |
4 |
|
T64 |
4 |
write_data_nack |
host |
28450 |
1 |
|
|
T11 |
241 |
|
T12 |
146 |
|
T13 |
3011 |
write_data_ack |
device |
868170 |
1 |
|
|
T6 |
24 |
|
T8 |
318 |
|
T9 |
90 |
write_data_ack |
host |
613691 |
1 |
|
|
T3 |
42 |
|
T4 |
324 |
|
T5 |
552 |
read_data_nack |
device |
64654 |
1 |
|
|
T6 |
3 |
|
T8 |
90 |
|
T9 |
43 |
read_data_nack |
host |
30088 |
1 |
|
|
T7 |
8 |
|
T14 |
64 |
|
T15 |
8 |
read_data_ack |
device |
500336 |
1 |
|
|
T6 |
20 |
|
T8 |
573 |
|
T9 |
68 |
read_data_ack |
host |
719714 |
1 |
|
|
T7 |
125 |
|
T14 |
429 |
|
T15 |
52 |
write_data |
device |
6516161 |
1 |
|
|
T6 |
198 |
|
T8 |
2314 |
|
T9 |
665 |
write_data |
host |
3681917 |
1 |
|
|
T3 |
252 |
|
T4 |
1958 |
|
T5 |
3324 |
read_data |
device |
3366581 |
1 |
|
|
T6 |
146 |
|
T8 |
3946 |
|
T9 |
681 |
read_data |
host |
5179937 |
1 |
|
|
T7 |
905 |
|
T14 |
3303 |
|
T15 |
412 |
write_addr_nack |
device |
32 |
1 |
|
|
T52 |
4 |
|
T53 |
4 |
|
T49 |
4 |
write_addr_nack |
host |
30319 |
1 |
|
|
T11 |
358 |
|
T12 |
292 |
|
T13 |
259 |
write_addr_ack |
device |
98410 |
1 |
|
|
T6 |
3 |
|
T8 |
57 |
|
T9 |
23 |
write_addr_ack |
host |
14806 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
59 |
read_addr_nack |
host |
70142 |
1 |
|
|
T11 |
30 |
|
T12 |
3134 |
|
T13 |
1052 |
read_addr_ack |
device |
68213 |
1 |
|
|
T6 |
3 |
|
T8 |
94 |
|
T9 |
51 |
read_addr_ack |
host |
21547 |
1 |
|
|
T7 |
11 |
|
T14 |
56 |
|
T15 |
8 |
write |
device |
117882 |
1 |
|
|
T6 |
4 |
|
T8 |
68 |
|
T9 |
24 |
write |
host |
17764 |
1 |
|
|
T3 |
4 |
|
T4 |
4 |
|
T5 |
76 |
read |
device |
58368 |
1 |
|
|
T6 |
3 |
|
T8 |
81 |
|
T9 |
42 |
read |
host |
18992 |
1 |
|
|
T7 |
12 |
|
T14 |
48 |
|
T15 |
6 |
addr |
device |
1056740 |
1 |
|
|
T6 |
49 |
|
T8 |
1092 |
|
T9 |
444 |
addr |
host |
190672 |
1 |
|
|
T3 |
18 |
|
T4 |
17 |
|
T5 |
337 |
rstart |
device |
91330 |
1 |
|
|
T6 |
3 |
|
T8 |
81 |
|
T9 |
44 |
rstart |
host |
1650 |
1 |
|
|
T7 |
6 |
|
T15 |
4 |
|
T11 |
7 |
start |
device |
34677 |
1 |
|
|
T6 |
3 |
|
T8 |
32 |
|
T9 |
2 |
start |
host |
26112 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
47 |
Summary for Cross num_rd_bytes_x_ip_mode_cp
Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
device |
sixtyfour |
1545 |
1 |
|
|
T190 |
24 |
|
T151 |
22 |
|
T260 |
3 |
device |
high |
82561 |
1 |
|
|
T71 |
53 |
|
T72 |
26 |
|
T190 |
1358 |
device |
mid |
379693 |
1 |
|
|
T8 |
180 |
|
T10 |
229 |
|
T44 |
176 |
device |
low |
2631980 |
1 |
|
|
T6 |
124 |
|
T8 |
3405 |
|
T9 |
333 |
device |
one |
368798 |
1 |
|
|
T6 |
24 |
|
T8 |
467 |
|
T9 |
168 |
host |
sixtyfour |
35939 |
1 |
|
|
T26 |
58 |
|
T78 |
4 |
|
T79 |
270 |
host |
high |
1263736 |
1 |
|
|
T26 |
1414 |
|
T78 |
547 |
|
T79 |
5604 |
host |
mid |
1710094 |
1 |
|
|
T14 |
566 |
|
T11 |
587 |
|
T26 |
5176 |
host |
low |
2231524 |
1 |
|
|
T7 |
934 |
|
T14 |
2403 |
|
T15 |
393 |
host |
one |
160440 |
1 |
|
|
T7 |
56 |
|
T14 |
418 |
|
T15 |
32 |
Summary for Cross num_wr_bytes_x_ip_mode_cp
Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
device |
sixtyfour |
10508 |
1 |
|
|
T52 |
114 |
|
T63 |
28 |
|
T189 |
24 |
device |
high |
313899 |
1 |
|
|
T10 |
441 |
|
T52 |
2350 |
|
T63 |
566 |
device |
mid |
886295 |
1 |
|
|
T10 |
1306 |
|
T71 |
326 |
|
T52 |
2526 |
device |
low |
4125676 |
1 |
|
|
T6 |
179 |
|
T8 |
1827 |
|
T9 |
472 |
device |
one |
564676 |
1 |
|
|
T6 |
22 |
|
T8 |
388 |
|
T9 |
130 |
host |
sixtyfour |
29863 |
1 |
|
|
T4 |
24 |
|
T155 |
26 |
|
T31 |
266 |
host |
high |
973068 |
1 |
|
|
T4 |
476 |
|
T155 |
486 |
|
T31 |
5412 |
host |
mid |
1144459 |
1 |
|
|
T4 |
544 |
|
T5 |
751 |
|
T7 |
254 |
host |
low |
1283664 |
1 |
|
|
T3 |
249 |
|
T4 |
476 |
|
T5 |
2395 |
host |
one |
103245 |
1 |
|
|
T3 |
24 |
|
T4 |
24 |
|
T5 |
333 |
Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp
Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
Stop_after_write_data_ack |
device |
6456 |
1 |
|
|
T8 |
2 |
|
T10 |
7 |
|
T45 |
3 |
Stop_after_write_data_ack |
host |
3304 |
1 |
|
|
T5 |
18 |
|
T7 |
1 |
|
T14 |
16 |
Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp
Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp
Uncovered bins
Stop_after_read_data_ack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
* |
* |
-- |
-- |
2 |
|
Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp
Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp
Element holes
Stop_after_write_data_Nack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
* |
[device] |
0 |
1 |
1 |
|
Covered bins
Stop_after_write_data_Nack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
Stop_after_write_data_Nack |
host |
63 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T13 |
4 |
Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp
Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
Stop_after_read_data_Nack |
device |
6004 |
1 |
|
|
T8 |
9 |
|
T10 |
4 |
|
T45 |
1 |
Stop_after_read_data_Nack |
host |
5762 |
1 |
|
|
T7 |
2 |
|
T14 |
15 |
|
T15 |
2 |
Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp
Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
Rstart_after_Address_Ack |
device |
20 |
1 |
|
|
T52 |
10 |
|
T53 |
10 |
|
- |
- |
Rstart_after_Address_Ack |
host |
7 |
1 |
|
|
T258 |
1 |
|
T261 |
1 |
|
T262 |
1 |
Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp
Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp
Bins
| | | | | | | | | | | | | |
Rstart_after_Address_Nack |
device |
8 |
1 |
|
|
T52 |
4 |
|
T53 |
4 |
|
- |
- |
Rstart_after_Address_Nack |
host |
57 |
1 |
|
|
T11 |
2 |
|
T12 |
2 |
|
T13 |
3 |
Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp
Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp
Element holes
Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
* |
[device] |
0 |
1 |
1 |
|
Excluded/Illegal bins
Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | STATUS | |
[auto[0]] |
[device , host] |
-- |
Excluded |
(2 bins) |
Covered bins
Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[1] |
host |
3 |
1 |
|
|
T142 |
2 |
|
T259 |
1 |