Summary for Variable address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for address_match
Bins
| | | | | | | | | | | | |
auto[0] |
12374832 |
1 |
|
|
T6 |
416 |
|
T8 |
8304 |
|
T9 |
1994 |
auto[1] |
11374004 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T3 |
322 |
Summary for Variable cp_address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_address_match
Excluded/Illegal bins
| | |
illegal |
0 |
Illegal |
ignore |
0 |
Excluded |
Covered bins
| | | | | | | | | | | | |
read_addr_no_match |
4245816 |
1 |
|
|
T6 |
181 |
|
T8 |
5267 |
|
T9 |
1092 |
read_addr_match |
6428664 |
1 |
|
|
T6 |
22 |
|
T7 |
1108 |
|
T8 |
268 |
write_addr_no_match |
7851972 |
1 |
|
|
T6 |
225 |
|
T8 |
3019 |
|
T9 |
880 |
write_addr_match |
4915230 |
1 |
|
|
T3 |
302 |
|
T4 |
2290 |
|
T5 |
4396 |
Summary for Variable cp_read_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_read_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
| | | | | | | | | | | | |
high |
2184221 |
1 |
|
|
T7 |
174 |
|
T8 |
1280 |
|
T9 |
223 |
med |
4132228 |
1 |
|
|
T6 |
108 |
|
T7 |
546 |
|
T8 |
1924 |
low |
4246197 |
1 |
|
|
T6 |
82 |
|
T7 |
379 |
|
T8 |
2251 |
all_zero |
111834 |
1 |
|
|
T6 |
13 |
|
T7 |
9 |
|
T8 |
80 |
Summary for Variable cp_write_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_write_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
| | | | | | | | | | | | |
high |
2596666 |
1 |
|
|
T3 |
68 |
|
T4 |
461 |
|
T5 |
550 |
med |
4964795 |
1 |
|
|
T3 |
147 |
|
T4 |
931 |
|
T5 |
2412 |
low |
5078615 |
1 |
|
|
T3 |
72 |
|
T4 |
855 |
|
T5 |
1387 |
all_zero |
127126 |
1 |
|
|
T3 |
15 |
|
T4 |
43 |
|
T5 |
47 |
Summary for Variable ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for ip_mode_cp
Bins
| | | | | | | | | | | | |
device |
13090695 |
1 |
|
|
T6 |
460 |
|
T8 |
8758 |
|
T9 |
2178 |
host |
10658141 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T3 |
322 |
Summary for Cross cross_address_match_x_ip_mode
Samples crossed: address_match ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_address_match_x_ip_mode
Bins
| | | | | | | | | | | | | |
auto[0] |
device |
12374726 |
1 |
|
|
T6 |
416 |
|
T8 |
8304 |
|
T9 |
1994 |
auto[0] |
host |
106 |
1 |
|
|
T100 |
1 |
|
T105 |
3 |
|
T191 |
2 |
auto[1] |
device |
715969 |
1 |
|
|
T6 |
44 |
|
T8 |
454 |
|
T9 |
184 |
auto[1] |
host |
10658035 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T3 |
322 |
Summary for Cross cross_write_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_write_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
| | | | | | | | | | | | | |
high |
device |
1682259 |
1 |
|
|
T6 |
3 |
|
T8 |
412 |
|
T9 |
84 |
high |
host |
914407 |
1 |
|
|
T3 |
68 |
|
T4 |
461 |
|
T5 |
550 |
med |
device |
3225262 |
1 |
|
|
T6 |
106 |
|
T8 |
1287 |
|
T9 |
490 |
med |
host |
1739533 |
1 |
|
|
T3 |
147 |
|
T4 |
931 |
|
T5 |
2412 |
low |
device |
3306129 |
1 |
|
|
T6 |
121 |
|
T8 |
1353 |
|
T9 |
352 |
low |
host |
1772486 |
1 |
|
|
T3 |
72 |
|
T4 |
855 |
|
T5 |
1387 |
all_zero |
device |
80423 |
1 |
|
|
T8 |
144 |
|
T9 |
27 |
|
T10 |
28 |
all_zero |
host |
46703 |
1 |
|
|
T3 |
15 |
|
T4 |
43 |
|
T5 |
47 |
Summary for Cross cross_read_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_read_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
| | | | | | | | | | | | | |
high |
device |
1682259 |
1 |
|
|
T6 |
3 |
|
T8 |
412 |
|
T9 |
84 |
high |
host |
914407 |
1 |
|
|
T3 |
68 |
|
T4 |
461 |
|
T5 |
550 |
med |
device |
3225262 |
1 |
|
|
T6 |
106 |
|
T8 |
1287 |
|
T9 |
490 |
med |
host |
1739533 |
1 |
|
|
T3 |
147 |
|
T4 |
931 |
|
T5 |
2412 |
low |
device |
3306129 |
1 |
|
|
T6 |
121 |
|
T8 |
1353 |
|
T9 |
352 |
low |
host |
1772486 |
1 |
|
|
T3 |
72 |
|
T4 |
855 |
|
T5 |
1387 |
all_zero |
device |
80423 |
1 |
|
|
T8 |
144 |
|
T9 |
27 |
|
T10 |
28 |
all_zero |
host |
46703 |
1 |
|
|
T3 |
15 |
|
T4 |
43 |
|
T5 |
47 |