Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33976940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8992581

1

T1

16

T2

39

T3

222

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42094333	1			T1	19		T2	101		T3	765
values[0x0]	436965	1			T1	11		T2	44		T3	13
values[0x1]	438223	1			T1	8		T2	53		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23733299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19236222

1

T1

18

T2

78

T3

404

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	192237	1			T3	5		T4	21		T8	5
valid_sources[0x01]	155226	1			T3	2		T4	16		T8	20
valid_sources[0x02]	165859	1			T3	7		T4	22		T8	32
valid_sources[0x03]	162166	1			T3	3		T4	10		T5	2
valid_sources[0x04]	161492	1			T3	4		T4	15		T8	46
valid_sources[0x05]	159515	1			T3	9		T4	25		T5	1
valid_sources[0x06]	150103	1			T3	1		T4	6		T5	3
valid_sources[0x07]	166468	1			T3	4		T4	10		T5	2
valid_sources[0x08]	180684	1			T4	14		T8	30		T33	33
valid_sources[0x09]	157486	1			T3	6		T4	11		T8	13
valid_sources[0x0a]	158848	1			T3	3		T4	3		T5	1
valid_sources[0x0b]	182094	1			T3	2		T4	3		T8	46
valid_sources[0x0c]	164386	1			T3	2		T4	22		T8	24
valid_sources[0x0d]	156728	1			T3	2		T4	5		T6	154
valid_sources[0x0e]	160729	1			T3	1		T4	4		T8	64
valid_sources[0x0f]	160523	1			T3	4		T4	2		T8	31
valid_sources[0x10]	200450	1			T3	4		T4	3		T8	28
valid_sources[0x11]	152309	1			T3	2		T4	13		T8	19
valid_sources[0x12]	164971	1			T3	1		T4	16		T8	12
valid_sources[0x13]	166737	1			T3	6		T4	30		T8	25
valid_sources[0x14]	160515	1			T3	2		T4	9		T8	9
valid_sources[0x15]	188753	1			T3	5		T4	16		T8	55
valid_sources[0x16]	156263	1			T3	8		T4	20		T5	1
valid_sources[0x17]	172602	1			T3	1		T4	13		T8	26
valid_sources[0x18]	171619	1			T4	11		T5	1		T8	62
valid_sources[0x19]	186490	1			T3	1		T4	13		T8	24
valid_sources[0x1a]	197783	1			T3	5		T4	8		T8	51
valid_sources[0x1b]	154348	1			T3	6		T4	18		T8	31
valid_sources[0x1c]	156908	1			T3	9		T4	9		T8	18
valid_sources[0x1d]	162110	1			T3	8		T4	14		T8	26
valid_sources[0x1e]	191231	1			T3	5		T4	11		T8	53
valid_sources[0x1f]	167547	1			T3	4		T4	11		T8	18
valid_sources[0x20]	170983	1			T3	2		T4	22		T8	47
valid_sources[0x21]	169289	1			T3	1		T4	12		T8	33
valid_sources[0x22]	238913	1			T3	1		T4	14		T8	19
valid_sources[0x23]	158956	1			T3	1		T4	5		T8	3
valid_sources[0x24]	164490	1			T3	1		T4	15		T8	15
valid_sources[0x25]	162504	1			T3	5		T4	8		T8	23
valid_sources[0x26]	158271	1			T3	7		T4	12		T8	47
valid_sources[0x27]	197508	1			T3	2		T4	15		T5	1
valid_sources[0x28]	168849	1			T3	5		T4	18		T8	24
valid_sources[0x29]	168737	1			T4	10		T8	51		T33	29
valid_sources[0x2a]	160464	1			T3	3		T4	17		T8	11
valid_sources[0x2b]	174166	1			T3	2		T4	20		T8	27
valid_sources[0x2c]	168519	1			T3	6		T4	14		T8	48
valid_sources[0x2d]	171850	1			T3	3		T4	8		T8	56
valid_sources[0x2e]	162470	1			T3	3		T4	10		T8	4
valid_sources[0x2f]	169020	1			T3	2		T4	6		T8	29
valid_sources[0x30]	178672	1			T3	2		T4	3		T8	66
valid_sources[0x31]	183621	1			T3	5		T4	10		T8	42
valid_sources[0x32]	166790	1			T3	4		T4	15		T8	33
valid_sources[0x33]	187947	1			T3	2		T4	12		T5	1
valid_sources[0x34]	149663	1			T3	3		T4	5		T8	40
valid_sources[0x35]	159837	1			T3	1		T4	13		T5	1
valid_sources[0x36]	181611	1			T3	7		T4	14		T8	38
valid_sources[0x37]	170930	1			T3	5		T4	15		T5	1
valid_sources[0x38]	174920	1			T3	1		T4	18		T8	17
valid_sources[0x39]	169977	1			T4	8		T8	24		T33	42
valid_sources[0x3a]	170946	1			T3	3		T4	26		T8	17
valid_sources[0x3b]	159846	1			T3	3		T4	6		T8	34
valid_sources[0x3c]	147802	1			T3	3		T4	20		T8	28
valid_sources[0x3d]	172860	1			T3	4		T4	11		T5	1
valid_sources[0x3e]	166246	1			T3	5		T4	14		T8	28
valid_sources[0x3f]	153659	1			T3	1		T4	13		T8	16
valid_sources[0x40]	170363	1			T3	2		T4	22		T8	45
valid_sources[0x41]	160642	1			T3	6		T4	5		T8	34
valid_sources[0x42]	169516	1			T3	10		T4	5		T8	17
valid_sources[0x43]	153200	1			T3	5		T4	6		T8	35
valid_sources[0x44]	186649	1			T3	7		T4	14		T8	22
valid_sources[0x45]	176126	1			T3	2		T4	2		T8	54
valid_sources[0x46]	186275	1			T3	2		T8	18		T33	28
valid_sources[0x47]	162881	1			T3	4		T4	10		T8	37
valid_sources[0x48]	160815	1			T3	6		T4	28		T8	15
valid_sources[0x49]	172183	1			T4	11		T8	34		T33	6
valid_sources[0x4a]	158674	1			T3	3		T4	17		T5	1
valid_sources[0x4b]	170580	1			T3	2		T4	5		T8	41
valid_sources[0x4c]	153981	1			T4	11		T8	24		T33	16
valid_sources[0x4d]	152262	1			T3	1		T4	20		T8	29
valid_sources[0x4e]	170448	1			T3	3		T4	3		T8	24
valid_sources[0x4f]	157321	1			T4	19		T8	8		T10	1
valid_sources[0x50]	163172	1			T3	5		T4	13		T8	26
valid_sources[0x51]	144682	1			T3	1		T4	22		T8	36
valid_sources[0x52]	171909	1			T3	2		T4	7		T8	13
valid_sources[0x53]	160159	1			T3	4		T4	29		T8	30
valid_sources[0x54]	163517	1			T3	1		T4	9		T8	41
valid_sources[0x55]	170744	1			T2	198		T3	3		T4	3
valid_sources[0x56]	160487	1			T3	2		T4	12		T8	15
valid_sources[0x57]	154214	1			T4	1		T8	20		T33	21
valid_sources[0x58]	199062	1			T3	2		T4	14		T5	1
valid_sources[0x59]	171917	1			T3	3		T4	19		T8	25
valid_sources[0x5a]	155617	1			T4	15		T8	43		T9	192
valid_sources[0x5b]	161300	1			T3	1		T4	8		T8	30
valid_sources[0x5c]	149449	1			T3	5		T4	12		T8	54
valid_sources[0x5d]	162230	1			T3	4		T4	20		T8	26
valid_sources[0x5e]	166356	1			T3	2		T4	5		T8	24
valid_sources[0x5f]	167025	1			T1	38		T3	1		T4	3
valid_sources[0x60]	143685	1			T3	2		T4	3		T8	72
valid_sources[0x61]	167793	1			T3	1		T4	12		T8	60
valid_sources[0x62]	151983	1			T3	1		T4	10		T8	15
valid_sources[0x63]	160154	1			T3	7		T4	17		T8	17
valid_sources[0x64]	178682	1			T3	2		T4	13		T8	23
valid_sources[0x65]	171133	1			T3	1		T4	6		T8	25
valid_sources[0x66]	159697	1			T3	1		T4	13		T8	28
valid_sources[0x67]	166119	1			T3	2		T4	3		T8	40
valid_sources[0x68]	169546	1			T4	8		T8	25		T33	14
valid_sources[0x69]	173102	1			T3	1		T4	10		T8	58
valid_sources[0x6a]	168664	1			T3	4		T4	9		T8	41
valid_sources[0x6b]	150092	1			T4	14		T8	11		T33	9
valid_sources[0x6c]	157523	1			T3	7		T4	7		T5	1
valid_sources[0x6d]	169393	1			T3	5		T4	5		T8	48
valid_sources[0x6e]	170181	1			T4	13		T8	46		T33	28
valid_sources[0x6f]	173062	1			T3	2		T4	4		T8	44
valid_sources[0x70]	167902	1			T3	5		T4	7		T8	31
valid_sources[0x71]	181101	1			T3	4		T4	8		T8	46
valid_sources[0x72]	161376	1			T4	18		T8	36		T10	1
valid_sources[0x73]	151563	1			T3	1		T4	9		T8	23
valid_sources[0x74]	185784	1			T4	10		T8	4		T33	57
valid_sources[0x75]	165190	1			T3	1		T4	6		T5	1
valid_sources[0x76]	159425	1			T3	5		T4	12		T8	13
valid_sources[0x77]	165468	1			T3	1		T4	22		T8	21
valid_sources[0x78]	179606	1			T3	5		T4	33		T8	44
valid_sources[0x79]	182730	1			T3	7		T8	50		T33	40
valid_sources[0x7a]	194434	1			T3	3		T4	11		T8	37
valid_sources[0x7b]	159216	1			T3	1		T4	8		T8	13
valid_sources[0x7c]	190303	1			T3	1		T4	12		T8	40
valid_sources[0x7d]	152286	1			T4	8		T8	5		T10	2
valid_sources[0x7e]	160628	1			T3	2		T4	12		T8	26
valid_sources[0x7f]	181790	1			T3	1		T4	7		T8	64
valid_sources[0x80]	170791	1			T3	2		T4	15		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8609015

1

T1

9

T2

1

T3

208

values[0x0]

all_enables

biggest_size

228624

1

T1

7

T2

23

T3

9

values[0x1]

all_enables

biggest_size

154942

1

T2

15

T3

5

T4

72