Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29776827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8455351

1

T1

16

T2

36

T3

384

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37407810	1			T1	20		T2	78		T3	1442
values[0x0]	411581	1			T1	14		T2	40		T3	34
values[0x1]	412787	1			T1	9		T2	33		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20837959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17394219

1

T1

18

T2

74

T3

713

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	141825	1			T3	2		T4	2		T5	18
valid_sources[0x01]	146363	1			T3	3		T4	8		T5	19
valid_sources[0x02]	144229	1			T3	5		T4	8		T5	5
valid_sources[0x03]	153728	1			T3	3		T4	7		T5	7
valid_sources[0x04]	162081	1			T3	8		T4	3		T5	12
valid_sources[0x05]	135345	1			T3	6		T4	7		T5	18
valid_sources[0x06]	141976	1			T3	6		T4	11		T5	10
valid_sources[0x07]	154351	1			T3	5		T4	8		T5	16
valid_sources[0x08]	151452	1			T3	7		T4	6		T5	11
valid_sources[0x09]	148672	1			T3	8		T4	4		T5	16
valid_sources[0x0a]	156661	1			T3	12		T4	12		T5	10
valid_sources[0x0b]	132358	1			T3	10		T4	6		T5	7
valid_sources[0x0c]	150875	1			T3	8		T4	12		T5	9
valid_sources[0x0d]	176527	1			T3	6		T4	5		T5	8
valid_sources[0x0e]	150751	1			T2	6		T3	7		T4	6
valid_sources[0x0f]	140934	1			T2	8		T3	5		T4	10
valid_sources[0x10]	148600	1			T2	3		T3	4		T4	9
valid_sources[0x11]	154134	1			T1	4		T3	9		T4	3
valid_sources[0x12]	138011	1			T3	4		T4	3		T5	13
valid_sources[0x13]	154017	1			T3	8		T4	8		T5	12
valid_sources[0x14]	138766	1			T3	6		T4	5		T5	12
valid_sources[0x15]	146629	1			T2	9		T3	8		T4	5
valid_sources[0x16]	148367	1			T3	4		T4	11		T5	8
valid_sources[0x17]	144080	1			T3	5		T4	6		T5	13
valid_sources[0x18]	156376	1			T3	3		T4	17		T5	17
valid_sources[0x19]	143507	1			T3	9		T4	3		T5	17
valid_sources[0x1a]	130081	1			T3	5		T4	7		T5	12
valid_sources[0x1b]	153423	1			T4	2		T5	19		T7	3
valid_sources[0x1c]	171513	1			T3	4		T4	4		T5	13
valid_sources[0x1d]	159360	1			T3	7		T4	10		T5	6
valid_sources[0x1e]	136246	1			T3	4		T4	8		T5	14
valid_sources[0x1f]	143794	1			T3	2		T4	9		T5	12
valid_sources[0x20]	131599	1			T3	1		T4	4		T5	19
valid_sources[0x21]	143779	1			T3	3		T4	10		T5	18
valid_sources[0x22]	145514	1			T3	9		T4	3		T5	7
valid_sources[0x23]	142457	1			T3	8		T4	9		T5	25
valid_sources[0x24]	138617	1			T3	10		T4	5		T5	18
valid_sources[0x25]	150629	1			T3	5		T4	5		T5	13
valid_sources[0x26]	144925	1			T3	5		T4	4		T5	20
valid_sources[0x27]	151321	1			T3	3		T4	10		T5	16
valid_sources[0x28]	139265	1			T3	7		T4	3		T5	14
valid_sources[0x29]	158565	1			T3	2		T4	4		T5	11
valid_sources[0x2a]	154433	1			T3	2		T4	6		T5	16
valid_sources[0x2b]	172761	1			T3	8		T4	3		T5	18
valid_sources[0x2c]	136210	1			T3	4		T4	4		T5	9
valid_sources[0x2d]	137388	1			T3	2		T4	11		T5	24
valid_sources[0x2e]	158641	1			T3	11		T4	11		T5	28
valid_sources[0x2f]	143098	1			T3	9		T4	1		T5	12
valid_sources[0x30]	135873	1			T3	7		T4	6		T5	39
valid_sources[0x31]	160263	1			T3	8		T4	7		T5	17
valid_sources[0x32]	141185	1			T3	9		T4	8		T5	16
valid_sources[0x33]	140346	1			T2	14		T3	6		T4	5
valid_sources[0x34]	138126	1			T3	12		T4	14		T5	12
valid_sources[0x35]	158844	1			T3	6		T4	9		T5	9
valid_sources[0x36]	165236	1			T1	4		T3	9		T4	4
valid_sources[0x37]	150915	1			T3	9		T4	4		T5	14
valid_sources[0x38]	145670	1			T3	7		T4	5		T5	20
valid_sources[0x39]	156472	1			T2	32		T3	7		T4	9
valid_sources[0x3a]	142393	1			T3	5		T4	7		T5	22
valid_sources[0x3b]	140777	1			T3	10		T4	5		T5	12
valid_sources[0x3c]	143923	1			T3	4		T4	1		T5	19
valid_sources[0x3d]	172337	1			T3	5		T4	4		T5	14
valid_sources[0x3e]	156556	1			T3	2		T4	1		T5	4
valid_sources[0x3f]	155379	1			T3	7		T4	3		T5	26
valid_sources[0x40]	142705	1			T3	3		T4	8		T5	15
valid_sources[0x41]	149409	1			T3	4		T4	13		T5	10
valid_sources[0x42]	138045	1			T3	4		T4	8		T5	13
valid_sources[0x43]	139203	1			T3	5		T4	13		T5	14
valid_sources[0x44]	143621	1			T3	3		T4	8		T5	5
valid_sources[0x45]	152018	1			T1	3		T3	8		T4	6
valid_sources[0x46]	145768	1			T3	7		T4	3		T5	7
valid_sources[0x47]	144419	1			T1	4		T3	3		T4	4
valid_sources[0x48]	144552	1			T3	5		T4	3		T5	18
valid_sources[0x49]	140008	1			T3	2		T4	4		T5	17
valid_sources[0x4a]	157688	1			T3	12		T4	8		T5	21
valid_sources[0x4b]	140088	1			T3	5		T4	2		T5	13
valid_sources[0x4c]	132560	1			T3	10		T4	10		T5	16
valid_sources[0x4d]	135203	1			T3	13		T4	4		T5	22
valid_sources[0x4e]	153469	1			T3	9		T4	9		T5	25
valid_sources[0x4f]	153711	1			T3	7		T4	8		T5	6
valid_sources[0x50]	133948	1			T3	1		T4	8		T5	19
valid_sources[0x51]	135761	1			T3	11		T4	2		T5	19
valid_sources[0x52]	144263	1			T3	4		T4	5		T5	12
valid_sources[0x53]	159310	1			T3	6		T4	2		T5	12
valid_sources[0x54]	137391	1			T3	12		T4	9		T5	15
valid_sources[0x55]	136559	1			T3	8		T4	3		T5	10
valid_sources[0x56]	147659	1			T3	4		T4	1		T5	11
valid_sources[0x57]	137270	1			T3	12		T4	6		T5	5
valid_sources[0x58]	153116	1			T3	10		T4	6		T5	13
valid_sources[0x59]	147001	1			T3	4		T4	2		T5	14
valid_sources[0x5a]	146679	1			T3	5		T4	10		T5	11
valid_sources[0x5b]	149952	1			T3	11		T4	9		T5	15
valid_sources[0x5c]	140365	1			T3	9		T4	2		T5	21
valid_sources[0x5d]	150265	1			T3	7		T4	14		T5	14
valid_sources[0x5e]	137656	1			T3	4		T4	11		T5	14
valid_sources[0x5f]	166281	1			T3	6		T4	9		T5	10
valid_sources[0x60]	151015	1			T3	8		T4	8		T5	14
valid_sources[0x61]	153434	1			T3	5		T4	8		T5	9
valid_sources[0x62]	139686	1			T3	4		T4	4		T5	9
valid_sources[0x63]	163100	1			T3	3		T4	3		T5	12
valid_sources[0x64]	148397	1			T2	13		T3	9		T4	8
valid_sources[0x65]	146047	1			T3	4		T4	1		T5	14
valid_sources[0x66]	147757	1			T3	7		T4	7		T5	7
valid_sources[0x67]	138057	1			T3	5		T4	7		T5	20
valid_sources[0x68]	244589	1			T3	4		T4	7		T5	13
valid_sources[0x69]	156495	1			T3	4		T4	8		T5	19
valid_sources[0x6a]	136193	1			T3	6		T4	6		T5	10
valid_sources[0x6b]	147784	1			T2	7		T3	10		T4	2
valid_sources[0x6c]	149296	1			T3	2		T4	10		T5	17
valid_sources[0x6d]	138098	1			T3	9		T4	12		T5	11
valid_sources[0x6e]	150321	1			T3	8		T4	5		T5	13
valid_sources[0x6f]	152448	1			T3	5		T4	6		T5	26
valid_sources[0x70]	168963	1			T1	1		T3	4		T4	9
valid_sources[0x71]	134321	1			T3	6		T5	25		T6	3
valid_sources[0x72]	155580	1			T3	14		T4	10		T5	16
valid_sources[0x73]	143084	1			T3	4		T4	7		T5	22
valid_sources[0x74]	168028	1			T3	9		T4	6		T5	18
valid_sources[0x75]	132315	1			T3	3		T4	13		T5	10
valid_sources[0x76]	153948	1			T3	3		T4	2		T5	23
valid_sources[0x77]	153847	1			T3	2		T4	12		T5	20
valid_sources[0x78]	162278	1			T3	4		T4	7		T5	15
valid_sources[0x79]	144230	1			T3	13		T4	9		T5	16
valid_sources[0x7a]	142982	1			T3	17		T4	8		T5	3
valid_sources[0x7b]	151395	1			T3	8		T4	10		T5	11
valid_sources[0x7c]	142715	1			T2	4		T3	2		T4	8
valid_sources[0x7d]	143830	1			T3	2		T4	4		T5	22
valid_sources[0x7e]	145362	1			T3	5		T4	6		T5	16
valid_sources[0x7f]	148473	1			T3	7		T4	6		T5	11
valid_sources[0x80]	141312	1			T3	13		T4	12		T5	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8087094

1

T1

13

T2

1

T3

344

values[0x0]

all_enables

biggest_size

217533

1

T1

3

T2

23

T3

17

values[0x1]

all_enables

biggest_size

150724

1

T2

12

T3

23

T4

17