Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_target_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	2099	1			T5	6		T14	5		T26	8
b2b_read_same_addr	312	1			T12	2		T31	1		T13	1
write_after_read_different_addr	2057	1			T5	5		T14	9		T15	1
write_after_read_same_addr	36	1			T164	1		T35	1		T286	1
read_after_write_different_addr	2035	1			T5	4		T14	10		T11	1
read_after_write_same_addr	30	1			T26	1		T287	1		T90	1
b2b_write_different_addr	2050	1			T5	2		T14	7		T15	1
b2b_write_same_addr	314	1			T5	1		T15	2		T11	3

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	5157	1			T73	2		T70	3		T75	57
b2b_read_same_addr	12779	1			T8	8		T9	9		T10	8
write_after_read_different_addr	5717	1			T8	11		T9	4		T10	5
write_after_read_same_addr	69	1			T44	1		T288	4		T289	4
read_after_write_different_addr	5688	1			T8	11		T9	4		T10	6
read_after_write_same_addr	66	1			T288	4		T289	4		T290	16
b2b_write_different_addr	5617	1			T45	5		T71	19		T47	16
b2b_write_same_addr	14029	1			T6	1		T8	13		T9	2