Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396343639	0	0	0
ctrl_rd_A	396343639	2756	0	0
host_fifo_config_rd_A	396343639	3902	0	0
host_nack_handler_timeout_rd_A	396343639	1680	0	0
host_timeout_ctrl_rd_A	396343639	1511	0	0
intr_enable_rd_A	396343639	4963	0	0
ovrd_rd_A	396343639	2789	0	0
target_fifo_config_rd_A	396343639	1735	0	0
target_id_rd_A	396343639	2089	0	0
target_timeout_ctrl_rd_A	396343639	1706	0	0
timeout_ctrl_rd_A	396343639	1947	0	0
timing0_rd_A	396343639	1763	0	0
timing1_rd_A	396343639	1813	0	0
timing2_rd_A	396343639	1685	0	0
timing3_rd_A	396343639	1712	0	0
timing4_rd_A	396343639	1754	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	2756	0	0
T100	8020	175	0	0
T101	1761	30	0	0
T102	9319	12	0	0
T103	2109	4	0	0
T104	13525	35	0	0
T105	14079	146	0	0
T106	5267	57	0	0
T107	7529	11	0	0
T108	51628	435	0	0
T109	15011	357	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	3902	0	0
T82	312738	128	0	0
T110	0	154	0	0
T111	0	125	0	0
T112	0	117	0	0
T113	0	190	0	0
T114	0	214	0	0
T115	0	126	0	0
T116	0	135	0	0
T117	0	163	0	0
T118	0	155	0	0
T119	12794	0	0	0
T120	1367	0	0	0
T121	80633	0	0	0
T122	22354	0	0	0
T123	249661	0	0	0
T124	8885	0	0	0
T125	18256	0	0	0
T126	365286	0	0	0
T127	182391	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1680	0	0
T100	8020	35	0	0
T101	1761	6	0	0
T102	9319	15	0	0
T103	2109	2	0	0
T104	13525	14	0	0
T105	14079	46	0	0
T106	5267	68	0	0
T107	7529	17	0	0
T108	51628	436	0	0
T128	3528	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1511	0	0
T100	8020	44	0	0
T102	9319	19	0	0
T103	2109	7	0	0
T104	13525	33	0	0
T105	14079	46	0	0
T106	5267	56	0	0
T107	7529	19	0	0
T108	51628	459	0	0
T109	15011	73	0	0
T128	3528	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	4963	0	0
T85	123840	0	0	0
T100	0	337	0	0
T101	0	4	0	0
T102	0	12	0	0
T103	0	3	0	0
T104	0	31	0	0
T105	0	270	0	0
T111	873863	45	0	0
T115	0	13	0	0
T129	0	16	0	0
T130	0	13	0	0
T131	142821	0	0	0
T132	2135	0	0	0
T133	10212	0	0	0
T134	40241	0	0	0
T135	2438	0	0	0
T136	12403	0	0	0
T137	10534	0	0	0
T138	68737	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	2789	0	0
T20	6905	0	0	0
T38	8632	0	0	0
T78	12713	0	0	0
T79	129597	0	0	0
T98	1465	49	0	0
T139	0	33	0	0
T140	0	71	0	0
T141	0	59	0	0
T142	0	54	0	0
T143	0	59	0	0
T144	0	64	0	0
T145	0	48	0	0
T146	0	66	0	0
T147	0	51	0	0
T148	22000	0	0	0
T149	73051	0	0	0
T150	54964	0	0	0
T151	115616	0	0	0
T152	113200	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1735	0	0
T100	8020	52	0	0
T101	1761	5	0	0
T102	9319	11	0	0
T103	2109	12	0	0
T104	13525	33	0	0
T105	14079	57	0	0
T106	5267	70	0	0
T107	7529	13	0	0
T108	51628	450	0	0
T128	3528	16	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	2089	0	0
T100	8020	52	0	0
T101	1761	11	0	0
T102	9319	23	0	0
T103	2109	5	0	0
T104	13525	22	0	0
T105	14079	157	0	0
T106	5267	52	0	0
T108	51628	413	0	0
T109	15011	154	0	0
T153	22857	131	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1706	0	0
T100	8020	65	0	0
T101	1761	6	0	0
T102	9319	26	0	0
T103	2109	12	0	0
T104	13525	33	0	0
T105	14079	68	0	0
T106	5267	48	0	0
T107	7529	8	0	0
T108	51628	441	0	0
T128	3528	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1947	0	0
T100	8020	60	0	0
T101	1761	2	0	0
T103	2109	8	0	0
T104	13525	41	0	0
T105	14079	86	0	0
T106	5267	48	0	0
T107	7529	25	0	0
T108	51628	438	0	0
T109	15011	210	0	0
T128	3528	17	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1763	0	0
T100	8020	52	0	0
T102	9319	17	0	0
T103	2109	7	0	0
T104	13525	24	0	0
T105	14079	62	0	0
T106	5267	39	0	0
T107	7529	2	0	0
T108	51628	445	0	0
T109	15011	127	0	0
T128	3528	2	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1813	0	0
T100	8020	64	0	0
T101	1761	6	0	0
T102	9319	10	0	0
T103	2109	8	0	0
T104	13525	66	0	0
T105	14079	80	0	0
T106	5267	59	0	0
T108	51628	456	0	0
T109	15011	100	0	0
T128	3528	23	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1685	0	0
T100	8020	60	0	0
T101	1761	7	0	0
T102	9319	36	0	0
T103	2109	4	0	0
T104	13525	17	0	0
T105	14079	66	0	0
T106	5267	66	0	0
T108	51628	412	0	0
T109	15011	110	0	0
T128	3528	40	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1712	0	0
T100	8020	58	0	0
T101	1761	11	0	0
T102	9319	12	0	0
T103	2109	12	0	0
T104	13525	42	0	0
T105	14079	57	0	0
T106	5267	50	0	0
T107	7529	14	0	0
T108	51628	463	0	0
T128	3528	17	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396343639	1754	0	0
T100	8020	86	0	0
T101	1761	5	0	0
T102	9319	19	0	0
T103	2109	12	0	0
T104	13525	32	0	0
T105	14079	71	0	0
T106	5267	96	0	0
T107	7529	1	0	0
T108	51628	460	0	0
T128	3528	5	0	0