Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445050578	0	0	0
ctrl_rd_A	445050578	4083	0	0
host_fifo_config_rd_A	445050578	5849	0	0
host_nack_handler_timeout_rd_A	445050578	2416	0	0
host_timeout_ctrl_rd_A	445050578	2315	0	0
intr_enable_rd_A	445050578	7022	0	0
ovrd_rd_A	445050578	2079	0	0
target_fifo_config_rd_A	445050578	2461	0	0
target_id_rd_A	445050578	3336	0	0
target_timeout_ctrl_rd_A	445050578	2523	0	0
timeout_ctrl_rd_A	445050578	3141	0	0
timing0_rd_A	445050578	2512	0	0
timing1_rd_A	445050578	2737	0	0
timing2_rd_A	445050578	2525	0	0
timing3_rd_A	445050578	2539	0	0
timing4_rd_A	445050578	2568	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	4083	0	0
T102	3435	33	0	0
T103	2984	25	0	0
T104	11028	128	0	0
T105	3946	10	0	0
T106	14159	387	0	0
T107	8648	3	0	0
T108	26753	218	0	0
T109	3041	33	0	0
T110	1931	35	0	0
T111	52557	446	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	5849	0	0
T20	0	109	0	0
T84	316170	148	0	0
T112	0	105	0	0
T113	0	231	0	0
T114	0	72	0	0
T115	0	237	0	0
T116	0	133	0	0
T117	0	136	0	0
T118	0	202	0	0
T119	0	245	0	0
T120	35928	0	0	0
T121	39297	0	0	0
T122	44936	0	0	0
T123	12337	0	0	0
T124	107259	0	0	0
T125	17052	0	0	0
T126	85808	0	0	0
T127	923951	0	0	0
T128	114586	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2416	0	0
T102	3435	15	0	0
T103	2984	17	0	0
T104	11028	121	0	0
T106	14159	88	0	0
T107	8648	26	0	0
T108	26753	220	0	0
T109	3041	7	0	0
T110	1931	3	0	0
T111	52557	427	0	0
T129	2574	2	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2315	0	0
T102	3435	34	0	0
T103	2984	10	0	0
T104	11028	151	0	0
T105	3946	10	0	0
T106	14159	77	0	0
T107	8648	13	0	0
T108	26753	202	0	0
T109	3041	13	0	0
T110	1931	8	0	0
T111	52557	480	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	7022	0	0
T20	867436	11	0	0
T102	0	9	0	0
T103	0	106	0	0
T104	0	140	0	0
T106	0	572	0	0
T107	0	26	0	0
T108	0	216	0	0
T109	0	9	0	0
T130	0	7	0	0
T131	0	16	0	0
T132	47023	0	0	0
T133	43233	0	0	0
T134	60992	0	0	0
T135	126350	0	0	0
T136	11864	0	0	0
T137	401224	0	0	0
T138	6322	0	0	0
T139	166943	0	0	0
T140	22079	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2079	0	0
T85	275963	0	0	0
T100	208811	0	0	0
T141	943	47	0	0
T142	0	64	0	0
T143	0	58	0	0
T144	0	57	0	0
T145	0	45	0	0
T146	0	39	0	0
T147	0	53	0	0
T148	0	54	0	0
T149	0	59	0	0
T150	0	55	0	0
T151	51234	0	0	0
T152	58751	0	0	0
T153	9029	0	0	0
T154	798786	0	0	0
T155	11798	0	0	0
T156	117237	0	0	0
T157	15248	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2461	0	0
T102	3435	28	0	0
T103	2984	11	0	0
T104	11028	96	0	0
T105	3946	20	0	0
T106	14159	129	0	0
T107	8648	22	0	0
T108	26753	230	0	0
T109	3041	21	0	0
T110	1931	14	0	0
T111	52557	413	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	3336	0	0
T102	3435	27	0	0
T103	2984	32	0	0
T104	11028	146	0	0
T106	14159	228	0	0
T107	8648	19	0	0
T108	26753	170	0	0
T109	3041	32	0	0
T110	1931	19	0	0
T111	52557	485	0	0
T129	2574	12	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2523	0	0
T102	3435	4	0	0
T103	2984	28	0	0
T104	11028	126	0	0
T106	14159	134	0	0
T107	8648	39	0	0
T108	26753	218	0	0
T109	3041	19	0	0
T110	1931	8	0	0
T111	52557	453	0	0
T129	2574	10	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	3141	0	0
T102	3435	25	0	0
T103	2984	29	0	0
T104	11028	148	0	0
T105	3946	7	0	0
T106	14159	137	0	0
T107	8648	44	0	0
T108	26753	255	0	0
T109	3041	23	0	0
T110	1931	18	0	0
T111	52557	488	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2512	0	0
T102	3435	22	0	0
T103	2984	20	0	0
T104	11028	108	0	0
T105	3946	7	0	0
T106	14159	120	0	0
T107	8648	36	0	0
T108	26753	210	0	0
T109	3041	5	0	0
T110	1931	9	0	0
T111	52557	431	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2737	0	0
T102	3435	37	0	0
T103	2984	21	0	0
T104	11028	133	0	0
T105	3946	11	0	0
T106	14159	116	0	0
T107	8648	20	0	0
T108	26753	242	0	0
T109	3041	3	0	0
T110	1931	16	0	0
T111	52557	480	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2525	0	0
T102	3435	6	0	0
T103	2984	12	0	0
T104	11028	144	0	0
T105	3946	6	0	0
T106	14159	107	0	0
T107	8648	27	0	0
T108	26753	172	0	0
T109	3041	7	0	0
T110	1931	17	0	0
T111	52557	411	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2539	0	0
T102	3435	13	0	0
T103	2984	19	0	0
T104	11028	115	0	0
T105	3946	11	0	0
T106	14159	109	0	0
T107	8648	22	0	0
T108	26753	224	0	0
T109	3041	22	0	0
T110	1931	6	0	0
T111	52557	470	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445050578	2568	0	0
T102	3435	14	0	0
T103	2984	21	0	0
T104	11028	122	0	0
T106	14159	114	0	0
T107	8648	6	0	0
T108	26753	223	0	0
T109	3041	4	0	0
T110	1931	13	0	0
T111	52557	479	0	0
T129	2574	5	0	0