KEYMGR Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	15.480s	462.745us	50	50	100.00
V1	random	keymgr_random	1.216m	2.455ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.160s	56.644us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.510s	112.755us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	34.550s	2.177ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.040s	517.682us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.180s	29.636us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.510s	112.755us	20	20	100.00
		keymgr_csr_aliasing	9.040s	517.682us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.248m	2.949ms	50	50	100.00
V2	sideload	keymgr_sideload	43.270s	2.510ms	50	50	100.00
		keymgr_sideload_kmac	36.040s	1.445ms	50	50	100.00
		keymgr_sideload_aes	1.215m	7.823ms	50	50	100.00
		keymgr_sideload_otbn	42.600s	18.290ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	41.420s	6.025ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	22.820s	3.340ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.040m	3.043ms	45	50	90.00
V2	invalid_sw_input	keymgr_sw_invalid_input	29.820s	4.089ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.340m	19.110ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.800s	1.003ms	49	50	98.00
V2	stress_all	keymgr_stress_all	14.328m	93.231ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.870s	41.889us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	18.500us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.770s	150.817us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.770s	150.817us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.160s	56.644us	5	5	100.00
		keymgr_csr_rw	1.510s	112.755us	20	20	100.00
		keymgr_csr_aliasing	9.040s	517.682us	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	231.698us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.160s	56.644us	5	5	100.00
		keymgr_csr_rw	1.510s	112.755us	20	20	100.00
		keymgr_csr_aliasing	9.040s	517.682us	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	231.698us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
		keymgr_tl_intg_err	31.830s	5.520ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	31.240s	1.605ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	31.240s	1.605ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	31.240s	1.605ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	31.240s	1.605ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	18.110s	2.159ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	31.830s	5.520ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	31.240s	1.605ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.248m	2.949ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.216m	2.455ms	50	50	100.00
		keymgr_csr_rw	1.510s	112.755us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.216m	2.455ms	50	50	100.00
		keymgr_csr_rw	1.510s	112.755us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.216m	2.455ms	50	50	100.00
		keymgr_csr_rw	1.510s	112.755us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	22.820s	3.340ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.340m	19.110ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.340m	19.110ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.216m	2.455ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.030s	4.231ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	58.980s	5.605ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	22.820s	3.340ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	58.980s	5.605ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	58.980s	5.605ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	58.980s	5.605ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.210s	3.128ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	58.980s	5.605ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.560s	300.433us	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1101	1110	99.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.09	98.09	98.35	100.00	99.08	98.38	91.66

Failure Buckets

UVM_ERROR (keymgr_scoreboard.sv:1012) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 5 failures:

Test keymgr_kmac_rsp_err has 5 failures.

14.keymgr_kmac_rsp_err.1573247225
Line 492, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  16039858 ps: (keymgr_scoreboard.sv:1012) [uvm_test_top.env.scoreboard] Check failed act != exp (1883794598742794865902657271306649404103391759364286773382431041131082589182005152000734242674208496768935525626202788478130337044550600134441129983803089684967871828390263049542529219524572743960173464112171957526237385554556539400729004535817367823126861311574525868527101845000506917012207344829484600739985243154032151205053812959101752784574023415555825019614038557834848102412731514308045361070391267066261896645728038 [0x4415491459cf6b63c9c04979646a1dea2a36fd8371e82661e68ebb04eb215fa23a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d7be946ecce74bf516eab675cbb7e93e52fe76af2a54557591f76a3c5ed575cfb4457ee620a657e8d7a10c11c8f2b2fbae19d818c6aaad47b7872bbab9162a1f5ba5c762e0bf78e8d16f2ccd53bcd5a307a051288e7d2de44b0c276818f32c1796d30813ca8cf771c11ca62115625726] vs 1883794598742794865902657271306649404103391759364286773382431041131082589182005152000734242674208496768935525626202788478130337044550600134441129983803089684967871828390263049542529219524572743960173464112171957526237385554556539400729004535817367823126861311574525868527101845000506917012207344829484600739985243154032151205053812959101752784574023415555825019614038557834848102412731514308045361070391267066261896645728038 [0x4415491459cf6b63c9c04979646a1dea2a36fd8371e82661e68ebb04eb215fa23a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d7be946ecce74bf516eab675cbb7e93e52fe76af2a54557591f76a3c5ed575cfb4457ee620a657e8d7a10c11c8f2b2fbae19d818c6aaad47b7872bbab9162a1f5ba5c762e0bf78e8d16f2ccd53bcd5a307a051288e7d2de44b0c276818f32c1796d30813ca8cf771c11ca62115625726]) cdi_type: Attestation
  
   DiversificationKey act: 0x7a051288e7d2de44b0c276818f32c1796d30813ca8cf771c11ca62115625726, exp: 0x7a051288e7d2de44b0c276818f32c1796d30813ca8cf771c11ca62115625726
   RomDigest act: 0xae19d818c6aaad47b7872bbab9162a1f5ba5c762e0bf78e8d16f2ccd53bcd5a3, exp: 0xae19d818c6aaad47b7872bbab9162a1f5ba5c762e0bf78e8d16f2ccd53bcd5a3
   HealthMeasurement act: 0xb4457ee620a657e8d7a10c11c8f2b2fb, exp: 0xb4457ee620a657e8d7a10c11c8f2b2fb

27.keymgr_kmac_rsp_err.1527855136
Line 323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  78461230 ps: (keymgr_scoreboard.sv:1012) [uvm_test_top.env.scoreboard] Check failed act != exp (7033301495859478210719971989213247264209521269305620604747939528713581945489673303378811013589502715386136339887436846306963800215989348636453652470384749527393931707276661460461680581241880191153499557568868759171425642471871525175517158782984609438902553241644600966426617525613207996735747726160685838937718478758575893740271876129669496142682230083063909848374531886336959172906447226515010229167782133706044406041799544 [0xfe31aa5cad0be187720e4079a1f262ba1e2a53a2cc2c91742a6892abf133d75a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 7033301495859478210719971989213247264209521269305620604747939528713581945489673303378811013589502715386136339887436846306963800215989348636453652470384749527393931707276661460461680581241880191153499557568868759171425642471871525175517158782984609438902553241644600966426617525613207996735747726160685838937718478758575893740271876129669496142682230083063909848374531886336959172906447226515010229167782133706044406041799544 [0xfe31aa5cad0be187720e4079a1f262ba1e2a53a2cc2c91742a6892abf133d75a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

Test keymgr_sync_async_fault_cross has 1 failures.

5.keymgr_sync_async_fault_cross.3571361149
Line 235, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest/run.log

  UVM_ERROR @   6367529 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   6367529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

47.keymgr_stress_all.4173938979
Line 291, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log

  UVM_ERROR @   7598887 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   7598887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 25.keymgr_stress_all_with_rand_reset.4280209168
    Line 341, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181078582 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2986777661 [0xb2069c3d] vs 2986777661 [0xb2069c3d])
  UVM_INFO @ 181078582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 39.keymgr_stress_all_with_rand_reset.3638706116
    Line 317, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34491213 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @  34491213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```