KEYMGR Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.150s	4.080ms	50	50	100.00
V1	random	keymgr_random	1.032m	4.779ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.540s	31.687us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	240.226us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.710s	9.303ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.990s	974.385us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.130s	57.946us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	240.226us	20	20	100.00
		keymgr_csr_aliasing	14.990s	974.385us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.328m	2.966ms	49	50	98.00
V2	sideload	keymgr_sideload	1.542m	19.270ms	49	50	98.00
		keymgr_sideload_kmac	56.410s	31.722ms	50	50	100.00
		keymgr_sideload_aes	1.045m	6.385ms	50	50	100.00
		keymgr_sideload_otbn	1.013m	7.448ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	45.350s	4.931ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	55.020s	2.678ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.524m	8.855ms	46	50	92.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.788m	10.339ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.519m	3.144ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.120s	792.346us	50	50	100.00
V2	stress_all	keymgr_stress_all	12.077m	56.043ms	45	50	90.00
V2	intr_test	keymgr_intr_test	1.090s	25.810us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.190s	110.353us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.670s	656.378us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.670s	656.378us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.540s	31.687us	5	5	100.00
		keymgr_csr_rw	1.560s	240.226us	20	20	100.00
		keymgr_csr_aliasing	14.990s	974.385us	5	5	100.00
		keymgr_same_csr_outstanding	4.280s	115.613us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.540s	31.687us	5	5	100.00
		keymgr_csr_rw	1.560s	240.226us	20	20	100.00
		keymgr_csr_aliasing	14.990s	974.385us	5	5	100.00
		keymgr_same_csr_outstanding	4.280s	115.613us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	sec_cm_additional_check	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
		keymgr_tl_intg_err	20.350s	659.035us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	19.620s	5.483ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	19.620s	5.483ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	19.620s	5.483ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	19.620s	5.483ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.430s	377.428us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	20.350s	659.035us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	19.620s	5.483ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.328m	2.966ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.032m	4.779ms	50	50	100.00
		keymgr_csr_rw	1.560s	240.226us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.032m	4.779ms	50	50	100.00
		keymgr_csr_rw	1.560s	240.226us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.032m	4.779ms	50	50	100.00
		keymgr_csr_rw	1.560s	240.226us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	55.020s	2.678ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.519m	3.144ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.519m	3.144ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.032m	4.779ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.720s	1.515ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	37.600s	2.803ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	55.020s	2.678ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	37.600s	2.803ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	37.600s	2.803ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	37.600s	2.803ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	25.100s	2.721ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	37.600s	2.803ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	14.180s	651.240us	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1094	1110	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	10	62.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.07	97.75	98.57	100.00	99.11	98.41	91.71

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_sideload has 1 failures.

15.keymgr_sideload.29672281623077655963480136117046545602217010563333701480087757614926915220596
Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload/latest/run.log

  UVM_ERROR @   7116103 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   7116103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

17.keymgr_stress_all.115042689901325193539624148756715816331028730864942488521544083833149592057227
Line 448, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log

  UVM_ERROR @  25019138 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  25019138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 1 failures.

20.keymgr_sw_invalid_input.26679838317420991544202006702069866393976565289025922917615291397931531482071
Line 409, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  19902391 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  19902391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

24.keymgr_lc_disable.24296485647059030814752273122972310188901284475598973050444046245088271772407
Line 378, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  68731157 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  68731157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

26.keymgr_cfg_regwen.31375428340374578945127544598908115824999168420411048612612836993861172643426
Line 386, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  22339718 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  22339718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 4 failures:

Test keymgr_kmac_rsp_err has 4 failures.

21.keymgr_kmac_rsp_err.112340473785146162501713762423136183256286429007836872919216728666588519180297
Line 479, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  60643194 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (4949652784324344377211254067613713505027075471162521874734802695177307900814288391373404232837762323315230175380736203149493494558453066597261581763375781496939775384119809160935299906085000934416059360964095382217136977853907443223378373491203427579035515129263111479433506514583597581250882699229019718347548579431758194643203357329271622270205819486753237870457053747648635403428644096429655900797958477778196967652673895 [0xb2e34911e3781c0524118035745a16d0bd1742be329863620000000098c9ddef3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9c2ba41a07800afcb1ef7634610b9acc9e1f25408c3955a593865f630453291a61b6654f590347e4cf98617693f01b553b3e3f73fbf214ad9dd107b8044de6337d7218df539589d34d5d34baa16729c6c07e8b226e47924ae4fa827e3550e35a59fe617272362af1f6791dd447b4d4967] vs 4949652784324344377211254067613713505027075471162521874734802695177307900814288391373404232837762323315230175380736203149493494558453066597261581763375781496939775384119809160935299906085000934416059360964095382217136977853907443223378373491203427579035515129263111479433506514583597581250882699229019718347548579431758194643203357329271622270205819486753237870457053747648635403428644096429655900797958477778196967652673895 [0xb2e34911e3781c0524118035745a16d0bd1742be329863620000000098c9ddef3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9c2ba41a07800afcb1ef7634610b9acc9e1f25408c3955a593865f630453291a61b6654f590347e4cf98617693f01b553b3e3f73fbf214ad9dd107b8044de6337d7218df539589d34d5d34baa16729c6c07e8b226e47924ae4fa827e3550e35a59fe617272362af1f6791dd447b4d4967]) cdi_type: Attestation
  
   DiversificationKey act: 0x7e8b226e47924ae4fa827e3550e35a59fe617272362af1f6791dd447b4d4967, exp: 0x7e8b226e47924ae4fa827e3550e35a59fe617272362af1f6791dd447b4d4967
   RomDigest act: 0xb3e3f73fbf214ad9dd107b8044de6337d7218df539589d34d5d34baa16729c6c, exp: 0xb3e3f73fbf214ad9dd107b8044de6337d7218df539589d34d5d34baa16729c6c
   HealthMeasurement act: 0x1b6654f590347e4cf98617693f01b553, exp: 0x1b6654f590347e4cf98617693f01b553

22.keymgr_kmac_rsp_err.59194597116763060321752967678431190231347848171966480800381873402770957209686
Line 466, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  45337987 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (2648353210718595382256294907472053483093692020812834109769134066291444717914120715159424958099978633286594587041391840204952392396196355876530530294696298750879603080634231486696432333249937671762390866841188928946560494601400776418407556360039432431188743995530122095158166134426117164003448965475916212933300774973918201342995714248269791667034950996574136562151968101135701031820488137131098955544987971645037267853634424 [0x5fb726bd85cc1d4aaffb04924f5b64af4e9461c08676c031eb5f78dabfa278963a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 2648353210718595382256294907472053483093692020812834109769134066291444717914120715159424958099978633286594587041391840204952392396196355876530530294696298750879603080634231486696432333249937671762390866841188928946560494601400776418407556360039432431188743995530122095158166134426117164003448965475916212933300774973918201342995714248269791667034950996574136562151968101135701031820488137131098955544987971645037267853634424 [0x5fb726bd85cc1d4aaffb04924f5b64af4e9461c08676c031eb5f78dabfa278963a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

... and 2 more failures.

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 0.keymgr_stress_all_with_rand_reset.47262989748982887078161119535562997991781155221693256126031590655106795783775
    Line 627, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111712381 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 111712381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.21738395685484311286534467579293235788367212836558128061650977688620648156861
    Line 746, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 397937435 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 397937435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:633) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 2 failures:
- Test keymgr_stress_all has 2 failures.
  - 16.keymgr_stress_all.98827899387841288655107723091964543318704942908995648029720041073303610410785
    Line 3632, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1366805450 ps: (keymgr_scoreboard.sv:633) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 1366805450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.keymgr_stress_all.5583832296281040520100130682225695761923590475455459775627247041956830970028
    Line 3157, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 5346884403 ps: (keymgr_scoreboard.sv:633) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 5346884403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 27.keymgr_stress_all.67667879576979337714536831889724345948006029788577736358979078901665200271930
    Line 1064, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 447799413 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3559365562 [0xd4279bba] vs 4169082929 [0xf87f2831]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @ 447799413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 34.keymgr_stress_all_with_rand_reset.36620378867598627076521784117521256676328135621742448647097058293790173179400
    Line 1171, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 523423050 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (259736284 [0xf7b42dc] vs 259736284 [0xf7b42dc])
  UVM_INFO @ 523423050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 48.keymgr_stress_all.45477565553194820382440832001787826952019524640336757356179129645132730297976
    Line 3056, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2021053203 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1620701946 [0x6099f2fa] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
  UVM_INFO @ 2021053203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```