KEYMGR Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.890s	1.541ms	50	50	100.00
V1	random	keymgr_random	50.450s	7.249ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.190s	441.190us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.660s	116.405us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.240s	1.166ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	18.390s	494.420us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.280s	271.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.660s	116.405us	20	20	100.00
		keymgr_csr_aliasing	18.390s	494.420us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.860m	2.128ms	49	50	98.00
V2	sideload	keymgr_sideload	1.084m	3.392ms	50	50	100.00
		keymgr_sideload_kmac	1.214m	4.654ms	50	50	100.00
		keymgr_sideload_aes	58.030s	5.284ms	50	50	100.00
		keymgr_sideload_otbn	1.021m	8.110ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	36.890s	4.198ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	26.850s	3.246ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.080m	10.345ms	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.403m	16.950ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.100m	4.660ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.740s	590.025us	50	50	100.00
V2	stress_all	keymgr_stress_all	12.334m	41.425ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.920s	14.865us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	16.881us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.700s	174.371us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.700s	174.371us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.190s	441.190us	5	5	100.00
		keymgr_csr_rw	1.660s	116.405us	20	20	100.00
		keymgr_csr_aliasing	18.390s	494.420us	5	5	100.00
		keymgr_same_csr_outstanding	4.390s	289.311us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.190s	441.190us	5	5	100.00
		keymgr_csr_rw	1.660s	116.405us	20	20	100.00
		keymgr_csr_aliasing	18.390s	494.420us	5	5	100.00
		keymgr_same_csr_outstanding	4.390s	289.311us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
		keymgr_tl_intg_err	13.080s	2.358ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	21.270s	6.657ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	21.270s	6.657ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	21.270s	6.657ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	21.270s	6.657ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.010s	1.431ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	13.080s	2.358ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	21.270s	6.657ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.860m	2.128ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	50.450s	7.249ms	50	50	100.00
		keymgr_csr_rw	1.660s	116.405us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	50.450s	7.249ms	50	50	100.00
		keymgr_csr_rw	1.660s	116.405us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	50.450s	7.249ms	50	50	100.00
		keymgr_csr_rw	1.660s	116.405us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	26.850s	3.246ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.100m	4.660ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.100m	4.660ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	50.450s	7.249ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	46.190s	4.339ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.109m	17.922ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	26.850s	3.246ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.109m	17.922ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.109m	17.922ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.109m	17.922ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	3.410m	11.927ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.109m	17.922ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.850s	440.768us	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1087	1110	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.07	98.06	98.26	100.00	99.11	98.41	91.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 0.keymgr_stress_all_with_rand_reset.8977382926878515927067896216951687509793464307568578263915169332128119664842
    Line 655, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 357686875 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 357686875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.20560316357777736550986230276823090037007013578014057136990091950009223449349
    Line 270, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 104045368 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 104045368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_cfg_regwen has 1 failures.

30.keymgr_cfg_regwen.89041776517654726991724412399083806055371355382072240895650569912392355671138
Line 774, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @ 399452295 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 399452295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

30.keymgr_stress_all.23309636354510587290233259672921318780416379405463680452765432177103971788094
Line 527, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 3534101044 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 3534101044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.keymgr_stress_all.31415727430836640830624611934149245760598618045998142687286263765321504971306
Line 1157, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 538982545 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 538982545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 2 failures:

Test keymgr_kmac_rsp_err has 2 failures.

10.keymgr_kmac_rsp_err.76830162911449509807576367032612755504016577365103496141513939916075389497934
Line 265, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 105775374 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (13869088684237589750254652523805745455607483863801036890679746459828093165537777673676646298413302974886366942187995618549352978946082093002165419734987556192739460847279491037323507763991289322339653917522990311668763766827472519817623988205376482773268720034198657295609071836724836973430828550405118008181699020267918627176491482427440827286527 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f94a426759ec7f553e1a2073321bed3d751abaef91fb5e6dd78c77bf286350ede98b3ad8a0a1e9916d3db5c1ddbb3ab61e77fcbcd95f5a0667817d1cf8a9dac742904ac52a2499211eb19df66103f571e399802e42fdb544b709a653080568d3b4c72867e1f9a2e2b783be2d80ae3543ff] vs 13869088684237589750254652523805745455607483863801036890679746459828093165537777673676646298413302974886366942187995618549352978946082093002165419734987556192739460847279491037323507763991289322339653917522990311668763766827472519817623988205376482773268720034198657295609071836724836973430828550405118008181699020267918627176491482427440827286527 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f94a426759ec7f553e1a2073321bed3d751abaef91fb5e6dd78c77bf286350ede98b3ad8a0a1e9916d3db5c1ddbb3ab61e77fcbcd95f5a0667817d1cf8a9dac742904ac52a2499211eb19df66103f571e399802e42fdb544b709a653080568d3b4c72867e1f9a2e2b783be2d80ae3543ff]) cdi_type: Attestation
  
   DiversificationKey act: 0x99802e42fdb544b709a653080568d3b4c72867e1f9a2e2b783be2d80ae3543ff, exp: 0x99802e42fdb544b709a653080568d3b4c72867e1f9a2e2b783be2d80ae3543ff
   RomDigest act: 0x77fcbcd95f5a0667817d1cf8a9dac742904ac52a2499211eb19df66103f571e3, exp: 0x77fcbcd95f5a0667817d1cf8a9dac742904ac52a2499211eb19df66103f571e3
   HealthMeasurement act: 0x8b3ad8a0a1e9916d3db5c1ddbb3ab61e, exp: 0x8b3ad8a0a1e9916d3db5c1ddbb3ab61e

23.keymgr_kmac_rsp_err.64796723669301974040271064285104367590864686731348113344668382419379360586483
Line 316, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  96662908 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (2387271317843096979323915074379628097032159890383927433125634340484371520457737336707353629602819460307094643570623193112391063912499024681593254475888910639511886906906136355630091317103714965724462636793858915611471153458066579704788416446446821549647994274350993482673218324363765427314729835976584886544109642393599464548321139725910359831181004264320791735315919378698131358386824324010581225869631968289223588294814584 [0x56479051b371a977ab1aab2127130bd0a45f23a58136c2d0cf2c75bf95958de43a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 2387271317843096979323915074379628097032159890383927433125634340484371520457737336707353629602819460307094643570623193112391063912499024681593254475888910639511886906906136355630091317103714965724462636793858915611471153458066579704788416446446821549647994274350993482673218324363765427314729835976584886544109642393599464548321139725910359831181004264320791735315919378698131358386824324010581225869631968289223588294814584 [0x56479051b371a977ab1aab2127130bd0a45f23a58136c2d0cf2c75bf95958de43a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

UVM_ERROR (cip_base_vseq.sv:719) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 26.keymgr_stress_all_with_rand_reset.65349932836358232988597661993405063489381823461135912540308158821079384936544
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173930691 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 173930691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```