KEYMGR Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	30.580s	5.565ms	50	50	100.00
V1	random	keymgr_random	52.100s	1.628ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.420s	94.006us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	67.974us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.190s	863.343us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	17.240s	491.435us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.920s	68.209us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	67.974us	20	20	100.00
		keymgr_csr_aliasing	17.240s	491.435us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.287m	4.835ms	50	50	100.00
V2	sideload	keymgr_sideload	38.310s	8.193ms	50	50	100.00
		keymgr_sideload_kmac	1.171m	3.254ms	50	50	100.00
		keymgr_sideload_aes	55.900s	3.081ms	50	50	100.00
		keymgr_sideload_otbn	1.411m	15.530ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.020s	3.502ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.240s	551.799us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	58.950s	7.246ms	42	50	84.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.467m	8.984ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.065m	13.868ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.490s	4.001ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.029m	12.996ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.000s	23.256us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	73.561us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.890s	185.885us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.890s	185.885us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.420s	94.006us	5	5	100.00
		keymgr_csr_rw	1.560s	67.974us	20	20	100.00
		keymgr_csr_aliasing	17.240s	491.435us	5	5	100.00
		keymgr_same_csr_outstanding	3.580s	89.847us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.420s	94.006us	5	5	100.00
		keymgr_csr_rw	1.560s	67.974us	20	20	100.00
		keymgr_csr_aliasing	17.240s	491.435us	5	5	100.00
		keymgr_same_csr_outstanding	3.580s	89.847us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
		keymgr_tl_intg_err	36.170s	1.264ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	15.620s	785.964us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	15.620s	785.964us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	15.620s	785.964us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	15.620s	785.964us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.080s	1.615ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	36.170s	1.264ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	15.620s	785.964us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.287m	4.835ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	52.100s	1.628ms	50	50	100.00
		keymgr_csr_rw	1.560s	67.974us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	52.100s	1.628ms	50	50	100.00
		keymgr_csr_rw	1.560s	67.974us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	52.100s	1.628ms	50	50	100.00
		keymgr_csr_rw	1.560s	67.974us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.240s	551.799us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.065m	13.868ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.065m	13.868ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	52.100s	1.628ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	35.570s	3.835ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.063m	2.592ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.240s	551.799us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.063m	2.592ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.063m	2.592ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.063m	2.592ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	34.310s	2.345ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.063m	2.592ms	49	50	98.00
V2S		TOTAL			163	165	98.79
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.090s	1.988ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1067	1110	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	4	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	98.14	98.24	100.00	99.11	98.41	91.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 28 failures:
- Test keymgr_stress_all_with_rand_reset has 28 failures.
  - 1.keymgr_stress_all_with_rand_reset.15124958090366905529367348102840485291320389106512907314863273136626721512431
    Line 280, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125371441 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 125371441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.83200328583051982941497096579587537413139856114216839823014160332869041767628
    Line 444, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116659186 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 116659186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 7 failures:

Test keymgr_kmac_rsp_err has 7 failures.

8.keymgr_kmac_rsp_err.31410744640313777113340199616378020363276323392050883862536658378482294204689
Line 411, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  51117618 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (6077416190894940619538502256857059272790611590969746106952308392500140225567322229917797446534762668873445742764612949875837289361593729676773839221037788525165645625563101177520682832175377256206826475209873718317960413772741166997721590408057355666041482337170702993182074047197196422142223088871173128494733225443452060938453690993486029251526506341933582895424859283198320330457757836394834228958893962258592855434281304 [0xdba59a44d5df1d83ced633f90000000074cd276424fbd2ae13d15759000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d59b56d12d40524d30b398b0a0d6c62035282b07cf4dd97cb672624e5ca1a09667fc41af695020e9a0f008660504389b23b9873a1af95b1e94fbed87d9e6f93f64e9ba175388f29c9f4e1ee3c02b2413904b5dddc3aee0670472fca2394258dff0e0c882a1b7d451844935f131854158] vs 6077416190894940619538502256857059272790611590969746106952308392500140225567322229917797446534762668873445742764612949875837289361593729676773839221037788525165645625563101177520682832175377256206826475209873718317960413772741166997721590408057355666041482337170702993182074047197196422142223088871173128494733225443452060938453690993486029251526506341933582895424859283198320330457757836394834228958893962258592855434281304 [0xdba59a44d5df1d83ced633f90000000074cd276424fbd2ae13d15759000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d59b56d12d40524d30b398b0a0d6c62035282b07cf4dd97cb672624e5ca1a09667fc41af695020e9a0f008660504389b23b9873a1af95b1e94fbed87d9e6f93f64e9ba175388f29c9f4e1ee3c02b2413904b5dddc3aee0670472fca2394258dff0e0c882a1b7d451844935f131854158]) cdi_type: Attestation
  
   DiversificationKey act: 0x904b5dddc3aee0670472fca2394258dff0e0c882a1b7d451844935f131854158, exp: 0x904b5dddc3aee0670472fca2394258dff0e0c882a1b7d451844935f131854158
   RomDigest act: 0x23b9873a1af95b1e94fbed87d9e6f93f64e9ba175388f29c9f4e1ee3c02b2413, exp: 0x23b9873a1af95b1e94fbed87d9e6f93f64e9ba175388f29c9f4e1ee3c02b2413
   HealthMeasurement act: 0x67fc41af695020e9a0f008660504389b, exp: 0x67fc41af695020e9a0f008660504389b

28.keymgr_kmac_rsp_err.18331371903992030312976398608880616265981122491272962812586402191026356713189
Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  49398188 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (213012978842781584645326571596401344083735704629126555674806512915287889485274603545964129023042873143869046896112587788841308057883115628333158843082519031365028242413943193092621133021788948832428010335686157852955143882835596413254725889611134640486949874974281327502708362936672202607995259963117782331708161930034969189892788280308584195779852640023396012548176545131605041574409053855313369260365517960627977435307680 [0x7b2d7e459210482d8cf0ab3804ab66a7dd8038566aa4d69808a5a28c1f973713a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9fd9efcfce8f406793871dfa5d974ac3ecee0c1f240613df6981410b7ecf566ca693e25ef7f75ba1295e9f2e0ae9f4626cb0d6381c8df7b3aa595fce011ab533b5cdc8e98b4f6c1b65484c0065420637ab4c774454736259a3bdb2f0ea72ca0173abcd1ddc8b2b097303e75bdef695ea0] vs 213012978842781584645326571596401344083735704629126555674806512915287889485274603545964129023042873143869046896112587788841308057883115628333158843082519031365028242413943193092621133021788948832428010335686157852955143882835596413254725889611134640486949874974281327502708362936672202607995259963117782331708161930034969189892788280308584195779852640023396012548176545131605041574409053855313369260365517960627977435307680 [0x7b2d7e459210482d8cf0ab3804ab66a7dd8038566aa4d69808a5a28c1f973713a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9fd9efcfce8f406793871dfa5d974ac3ecee0c1f240613df6981410b7ecf566ca693e25ef7f75ba1295e9f2e0ae9f4626cb0d6381c8df7b3aa595fce011ab533b5cdc8e98b4f6c1b65484c0065420637ab4c774454736259a3bdb2f0ea72ca0173abcd1ddc8b2b097303e75bdef695ea0]) cdi_type: Attestation
  
   DiversificationKey act: 0xb4c774454736259a3bdb2f0ea72ca0173abcd1ddc8b2b097303e75bdef695ea0, exp: 0xb4c774454736259a3bdb2f0ea72ca0173abcd1ddc8b2b097303e75bdef695ea0
   RomDigest act: 0xcb0d6381c8df7b3aa595fce011ab533b5cdc8e98b4f6c1b65484c0065420637a, exp: 0xcb0d6381c8df7b3aa595fce011ab533b5cdc8e98b4f6c1b65484c0065420637a
   HealthMeasurement act: 0x693e25ef7f75ba1295e9f2e0ae9f4626, exp: 0x693e25ef7f75ba1295e9f2e0ae9f4626

... and 5 more failures.

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 7.keymgr_stress_all_with_rand_reset.58928534332430788862725813733958917300485263676693366899773648506445589808693
    Line 1196, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2216041075 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2920096626 [0xae0d2372] vs 2920096626 [0xae0d2372])
  UVM_INFO @ 2216041075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.keymgr_stress_all_with_rand_reset.67410737073445275235944840004025966526247011628505323741122385787687571089636
    Line 1072, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 204280178 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3072415355 [0xb721567b] vs 3072415355 [0xb721567b])
  UVM_INFO @ 204280178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sideload_protect has 1 failures.
  - 9.keymgr_sideload_protect.11588662938427380396875173034955756777028890819655276254938747431664667709684
    Line 325, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @  10240202 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  10240202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 21.keymgr_stress_all.104975009878848230822381842987124422985674041249032226750930560697170546216355
    Line 657, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  84931462 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  84931462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_kmac_rsp_err has 1 failures.
  - 44.keymgr_kmac_rsp_err.5328161765889522907930676710584013810457221226777057789602837137544817881788
    Line 768, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @ 156013819 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 156013819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:81) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 8.keymgr_custom_cm.5169268261447325867198873391203977800405922902369934819817461952268377871090
    Line 441, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10450579729 ps: (keymgr_custom_cm_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10450579729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 20.keymgr_stress_all.84807941945539269533943002179248426152332755617813312799133399501671628881412
    Line 2297, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 624702639 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1577250529 [0x5e02eee1] vs 3320438586 [0xc5e9df3a]) reg name: keymgr_reg_block.sw_share1_output_4
  UVM_INFO @ 624702639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```