e3ca274e77
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 44.520s | 4.432ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.142m | 10.253ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.160s | 71.161us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 16.520s | 2.163ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.470s | 362.230us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.470s | 355.521us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.470s | 362.230us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.256m | 5.685ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 43.380s | 3.366ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.002m | 5.930ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.403m | 7.939ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 40.570s | 5.639ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 32.860s | 4.872ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 9.240s | 1.152ms | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 57.520s | 4.284ms | 46 | 50 | 92.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 36.990s | 1.519ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 41.340s | 6.450ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 18.320s | 2.541ms | 48 | 50 | 96.00 |
V2 | stress_all | keymgr_stress_all | 7.434m | 275.393ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.920s | 14.048us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.160s | 29.449us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.480s | 140.840us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.480s | 140.840us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.160s | 71.161us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.470s | 362.230us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.350s | 442.861us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.160s | 71.161us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.470s | 362.230us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.350s | 442.861us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 731 | 740 | 98.78 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 42.170s | 7.409ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 25.600s | 4.582ms | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 25.600s | 4.582ms | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 25.600s | 4.582ms | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 25.600s | 4.582ms | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 13.890s | 799.935us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 42.170s | 7.409ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 25.600s | 4.582ms | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.256m | 5.685ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.142m | 10.253ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.142m | 10.253ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.142m | 10.253ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.660s | 120.851us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 9.240s | 1.152ms | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 41.340s | 6.450ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 41.340s | 6.450ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.142m | 10.253ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 23.640s | 1.870ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 53.200s | 10.281ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 9.240s | 1.152ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 53.200s | 10.281ms | 48 | 50 | 96.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 53.200s | 10.281ms | 48 | 50 | 96.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 53.200s | 10.281ms | 48 | 50 | 96.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 32.430s | 1.652ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 53.200s | 10.281ms | 48 | 50 | 96.00 |
V2S | TOTAL | 163 | 165 | 98.79 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 30.240s | 726.709us | 26 | 50 | 52.00 |
V3 | TOTAL | 26 | 50 | 52.00 | |||
TOTAL | 1075 | 1110 | 96.85 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 11 | 68.75 |
V2S | 6 | 6 | 5 | 83.33 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.79 | 99.07 | 98.06 | 98.43 | 100.00 | 99.11 | 98.41 | 91.49 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 14 failures:
1.keymgr_stress_all_with_rand_reset.6046652630714705063473367378715525258884109649145655740373481529022329796991
Line 379, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1109763690 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1109763690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.64893381868300692649640000742191501695636063819132604452927124753741511465943
Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 606508679 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 606508679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * [])` has 6 failures:
3.keymgr_stress_all_with_rand_reset.37429706737891600369750532426505112118693213533775383300412412717332096573764
Line 1256, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1131736874 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3525006595 [0xd21b5503] vs 3525006595 [0xd21b5503])
UVM_INFO @ 1131736874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.keymgr_stress_all_with_rand_reset.100104767477268366231748575826034868356452048607690299966647056804786634352386
Line 774, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 748061734 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1426426979 [0x55058c63] vs 1426426979 [0x55058c63])
UVM_INFO @ 748061734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 4 failures:
Test keymgr_kmac_rsp_err has 1 failures.
7.keymgr_kmac_rsp_err.60611411466363357064653877340620854165669033112444624749974987208430519096416
Line 398, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 9487708 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 9487708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
10.keymgr_stress_all.54394705587262542045319123610546992407892479824381151222958208112891969714004
Line 2262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log
UVM_ERROR @ 2627470399 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 2627470399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_hwsw_invalid_input has 1 failures.
37.keymgr_hwsw_invalid_input.73393049700528272600125337446941477188983171248017103214268270595997956751770
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 6288574 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 6288574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
41.keymgr_stress_all_with_rand_reset.49690291720429366203582202872709554888216192074441650153113073619933097715171
Line 880, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 223468353 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 223468353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation
has 3 failures:
26.keymgr_kmac_rsp_err.95691271209190220863666553809681264848018842145033474917114293979114356764788
Line 665, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 126443410 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (3548630623071929131523244849891083572743616899174838000235608606444235141106033348204959535967446354535688604714751175222294306114227824259896968697777936249625760682537908830292086163479702126287894838409357601433751020725990531595680124791980285715359424934740113483469574030966808634316844878179834498787024558156193577915547465363992023650363054910270745635155300075434338026052288931779228730981612308911582272724350698 [0x8040b7b70676bf4698fd01ec57b13476d036cabb8f724c2a4144d9b8bdf860773a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9b89c10d4b76a6ba1bf8c8a19c9297b3dc63fa72084393cb8a5171144a6ae23f66184d3faef41680dff947f9531268f90f20b9ed9fd6e18cf98f9c4d73b207dc1617a48adddef91864ece764137ba4d60b8345aa7bd4df08626862a2611d45ab6b80318ea3531aa4cc15c0ff36d1736ea] vs 3548630623071929131523244849891083572743616899174838000235608606444235141106033348204959535967446354535688604714751175222294306114227824259896968697777936249625760682537908830292086163479702126287894838409357601433751020725990531595680124791980285715359424934740113483469574030966808634316844878179834498787024558156193577915547465363992023650363054910270745635155300075434338026052288931779228730981612308911582272724350698 [0x8040b7b70676bf4698fd01ec57b13476d036cabb8f724c2a4144d9b8bdf860773a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9b89c10d4b76a6ba1bf8c8a19c9297b3dc63fa72084393cb8a5171144a6ae23f66184d3faef41680dff947f9531268f90f20b9ed9fd6e18cf98f9c4d73b207dc1617a48adddef91864ece764137ba4d60b8345aa7bd4df08626862a2611d45ab6b80318ea3531aa4cc15c0ff36d1736ea]) cdi_type: Attestation
DiversificationKey act: 0xb8345aa7bd4df08626862a2611d45ab6b80318ea3531aa4cc15c0ff36d1736ea, exp: 0xb8345aa7bd4df08626862a2611d45ab6b80318ea3531aa4cc15c0ff36d1736ea
RomDigest act: 0xf20b9ed9fd6e18cf98f9c4d73b207dc1617a48adddef91864ece764137ba4d60, exp: 0xf20b9ed9fd6e18cf98f9c4d73b207dc1617a48adddef91864ece764137ba4d60
HealthMeasurement act: 0x6184d3faef41680dff947f9531268f90, exp: 0x6184d3faef41680dff947f9531268f90
29.keymgr_kmac_rsp_err.54502920655783461091379283567887245682748423386531305231761931097299684437820
Line 332, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 66270334 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (997902407829259571391283843315516116314196646768303834018689715850193964165637419172519203141328885030903068383903262195216495264408345397903099070174626850171264686259341206782508815804986405292103834950119262506025763839694670836072985589759637043596938321845807965991382964042947568479505076968557228574092629956134916985685377995324458437261205465582109260697036625919756969062833763912053452588045583307631480 [0x9ae6a2cf9ca878e68cabc19900000000023a858000000000a2dd424d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 997902407829259571391283843315516116314196646768303834018689715850193964165637419172519203141328885030903068383903262195216495264408345397903099070174626850171264686259341206782508815804986405292103834950119262506025763839694670836072985589759637043596938321845807965991382964042947568479505076968557228574092629956134916985685377995324458437261205465582109260697036625919756969062833763912053452588045583307631480 [0x9ae6a2cf9ca878e68cabc19900000000023a858000000000a2dd424d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received!
has 2 failures:
14.keymgr_sync_async_fault_cross.2369670123996330981675540376097778576364251489911378955366615556334034169355
Line 307, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 461600669 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 461600669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.keymgr_sync_async_fault_cross.104685380443290863878234297091762752371007659787817035121836902964166567466363
Line 323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 74170184 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 74170184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 2 failures:
31.keymgr_stress_all_with_rand_reset.75432311811414395030103167728361494543149965689632000450693742919095467846956
Line 424, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 133360610 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 133360610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.keymgr_stress_all_with_rand_reset.29221057186140122466938806756219495628309433791256825125173124840438884608559
Line 364, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 884830106 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 884830106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
16.keymgr_stress_all_with_rand_reset.60756478339693749838623088722203194258523518259708026078335857924760977976552
Line 715, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 304416108 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 304416108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred!
has 1 failures:
21.keymgr_custom_cm.12915571180794514578800788370555405077180541098945381421054821755018081285226
Line 357, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_custom_cm/latest/run.log
UVM_FATAL @ 10280520981 ps: (keymgr_custom_cm_vseq.sv:45) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
UVM_INFO @ 10280520981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (keymgr_custom_cm_vseq.sv:81) [keymgr_custom_cm_vseq] wait timeout occurred!
has 1 failures:
24.keymgr_custom_cm.70599692195263874010873843920887837732827224346358622757898490639371413412466
Line 280, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_custom_cm/latest/run.log
UVM_FATAL @ 10114569496 ps: (keymgr_custom_cm_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
UVM_INFO @ 10114569496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
26.keymgr_cfg_regwen.113974120600200442279370627801959308444723894672381217776137911870706271390490
Line 428, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 12696033 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 12696033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---