KEYMGR Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	41.270s	2.090ms	50	50	100.00
V1	random	keymgr_random	1.110m	17.119ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.220s	20.859us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.330s	56.761us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.660s	3.427ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.700s	375.672us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.660s	37.532us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.330s	56.761us	20	20	100.00
		keymgr_csr_aliasing	8.700s	375.672us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.795m	1.944ms	50	50	100.00
V2	sideload	keymgr_sideload	41.300s	1.682ms	50	50	100.00
		keymgr_sideload_kmac	1.172m	9.105ms	50	50	100.00
		keymgr_sideload_aes	27.820s	1.051ms	50	50	100.00
		keymgr_sideload_otbn	1.141m	2.062ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	47.330s	14.654ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	46.020s	2.666ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.483m	15.278ms	46	50	92.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.456m	2.622ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.360m	16.172ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.040s	732.934us	50	50	100.00
V2	stress_all	keymgr_stress_all	7.059m	100.593ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.930s	12.363us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	13.045us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.480s	142.818us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.480s	142.818us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.220s	20.859us	5	5	100.00
		keymgr_csr_rw	1.330s	56.761us	20	20	100.00
		keymgr_csr_aliasing	8.700s	375.672us	5	5	100.00
		keymgr_same_csr_outstanding	4.140s	188.554us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.220s	20.859us	5	5	100.00
		keymgr_csr_rw	1.330s	56.761us	20	20	100.00
		keymgr_csr_aliasing	8.700s	375.672us	5	5	100.00
		keymgr_same_csr_outstanding	4.140s	188.554us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
		keymgr_tl_intg_err	1.326m	2.546ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	35.720s	3.505ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	35.720s	3.505ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	35.720s	3.505ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	35.720s	3.505ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.200s	445.218us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.326m	2.546ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	35.720s	3.505ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.795m	1.944ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.110m	17.119ms	50	50	100.00
		keymgr_csr_rw	1.330s	56.761us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.110m	17.119ms	50	50	100.00
		keymgr_csr_rw	1.330s	56.761us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.110m	17.119ms	50	50	100.00
		keymgr_csr_rw	1.330s	56.761us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	46.020s	2.666ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.360m	16.172ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.360m	16.172ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.110m	17.119ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	26.800s	3.037ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.119m	10.195ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	46.020s	2.666ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.119m	10.195ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.119m	10.195ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.119m	10.195ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	56.540s	10.695ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.119m	10.195ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.880s	2.773ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1076	1110	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.07	98.22	98.32	100.00	99.11	98.41	91.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.62021187100872404256539866049120214039097337591616026781472828574696150235667
    Line 445, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119689415 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 119689415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.keymgr_stress_all_with_rand_reset.5560644032321415523169471760887677370792469266400317432282005636625723991404
    Line 653, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 221861788 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 221861788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 4 failures:

Test keymgr_kmac_rsp_err has 4 failures.

1.keymgr_kmac_rsp_err.42499463154298644424179238934559798627432931871654906328518525124800245134175
Line 391, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  63458308 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (13869088684237589750254652523805745455607483863801036890679746459828093165537643367058763059215761105571359656532483971383073314010380959783321951881930781834183527957453144460719048557339870650074943635445600162495434650192907837354701924527533912447631773605343900695148171420107518552725534266662175609005585822993871917688115399215435540236500 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9092d65bd48b8bf8d4996da58de4feb55426d96a541a664b348bfdda06353377c4a99c14f4aa94bb6b2e88d01cae80db39e1031494366f09816db38336b832421ccb26e6d1f780a96cb2adb4985095924013d1d8fcfa3dc774944831571e8ee9dc031327944e832f8a582dd069d2688d4] vs 13869088684237589750254652523805745455607483863801036890679746459828093165537643367058763059215761105571359656532483971383073314010380959783321951881930781834183527957453144460719048557339870650074943635445600162495434650192907837354701924527533912447631773605343900695148171420107518552725534266662175609005585822993871917688115399215435540236500 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9092d65bd48b8bf8d4996da58de4feb55426d96a541a664b348bfdda06353377c4a99c14f4aa94bb6b2e88d01cae80db39e1031494366f09816db38336b832421ccb26e6d1f780a96cb2adb4985095924013d1d8fcfa3dc774944831571e8ee9dc031327944e832f8a582dd069d2688d4]) cdi_type: Attestation
  
   DiversificationKey act: 0x13d1d8fcfa3dc774944831571e8ee9dc031327944e832f8a582dd069d2688d4, exp: 0x13d1d8fcfa3dc774944831571e8ee9dc031327944e832f8a582dd069d2688d4
   RomDigest act: 0x9e1031494366f09816db38336b832421ccb26e6d1f780a96cb2adb4985095924, exp: 0x9e1031494366f09816db38336b832421ccb26e6d1f780a96cb2adb4985095924
   HealthMeasurement act: 0x4a99c14f4aa94bb6b2e88d01cae80db3, exp: 0x4a99c14f4aa94bb6b2e88d01cae80db3

3.keymgr_kmac_rsp_err.79744317527305851134336859030652463542651210750830176679373750209242292821323
Line 384, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 389237173 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (3686974593973063669342746802967231550505452335636598328843590739156644796003485130542871789564569267555526307459946126953490499401000204594638426891136743596483924206092762885203469596904217470104628539297780005453581238603552259204789368244047484956400389421708924793224158004246430138051342883925231276243703136973594796650207492809749667606494559869233531528639737204648627668542316060935916311390784540481355408663249117 [0x8540b4ecf9beb4a6d67e21f5af9894325ec52433f579797c4c15ada08cf8c9893a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f980bd2fcb641137b1884b546d5dbca86abe4cf086f38b73616f0c867d07188e24ba678b0522239490cf322fcfd4938449c456a82e574d5ba3a7fd45c0867dc65b73035f4e6d695b7813beb8a9accae499316dc23abc6aa90280c86bdbd125bcb1deaf6c028711990e4f2fbc949f0600dd] vs 3686974593973063669342746802967231550505452335636598328843590739156644796003485130542871789564569267555526307459946126953490499401000204594638426891136743596483924206092762885203469596904217470104628539297780005453581238603552259204789368244047484956400389421708924793224158004246430138051342883925231276243703136973594796650207492809749667606494559869233531528639737204648627668542316060935916311390784540481355408663249117 [0x8540b4ecf9beb4a6d67e21f5af9894325ec52433f579797c4c15ada08cf8c9893a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f980bd2fcb641137b1884b546d5dbca86abe4cf086f38b73616f0c867d07188e24ba678b0522239490cf322fcfd4938449c456a82e574d5ba3a7fd45c0867dc65b73035f4e6d695b7813beb8a9accae499316dc23abc6aa90280c86bdbd125bcb1deaf6c028711990e4f2fbc949f0600dd]) cdi_type: Attestation
  
   DiversificationKey act: 0x316dc23abc6aa90280c86bdbd125bcb1deaf6c028711990e4f2fbc949f0600dd, exp: 0x316dc23abc6aa90280c86bdbd125bcb1deaf6c028711990e4f2fbc949f0600dd
   RomDigest act: 0xc456a82e574d5ba3a7fd45c0867dc65b73035f4e6d695b7813beb8a9accae499, exp: 0xc456a82e574d5ba3a7fd45c0867dc65b73035f4e6d695b7813beb8a9accae499
   HealthMeasurement act: 0xba678b0522239490cf322fcfd4938449, exp: 0xba678b0522239490cf322fcfd4938449

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sideload_otbn has 1 failures.
  - 12.keymgr_sideload_otbn.40125829804527182317512028423108073759126411612442641698118327547632498944220
    Line 260, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @  22956802 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  22956802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 14.keymgr_stress_all.95586776830142577419643151511236031860623375091263382552376850596555447168577
    Line 3004, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1470333756 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 1470333756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sw_invalid_input has 1 failures.
  - 42.keymgr_sw_invalid_input.4882520511919446078203848988140752092438940948095039871074669133166253084464
    Line 426, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @  59939558 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  59939558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 42.keymgr_stress_all_with_rand_reset.67209295343838815786369577221236971183636964359998248858478496157029644388662
    Line 701, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 422892136 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3891251218 [0xe7efc812] vs 3891251218 [0xe7efc812])
  UVM_INFO @ 422892136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.keymgr_stress_all_with_rand_reset.73094565842661199760957323698967026068800019651419968415163980060836544779678
    Line 2044, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1593068531 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3011099610 [0xb379bbda] vs 3011099610 [0xb379bbda])
  UVM_INFO @ 1593068531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:81) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 32.keymgr_custom_cm.86894575455910736705471947580000656081370038395069997668227013414527472034141
    Line 545, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10194634009 ps: (keymgr_custom_cm_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10194634009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 45.keymgr_stress_all.19656259901962296491887794644694774895240237370118937964239487600984580036405
    Line 3128, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 10170125236 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1006189415 [0x3bf93b67] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
  UVM_INFO @ 10170125236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```