Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	95.95	98.39	99.96		95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.04	95.95	98.39	99.96		95.92	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	95.95	98.39	99.96		95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.90	99.07	98.14	98.69	100.00	99.11	98.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	98.15	100.00	94.44			100.00
u_checks	100.00	100.00					100.00
u_ctrl	97.22	99.70	95.19	95.70	100.00	98.60	94.12
u_fault_alert	100.00			100.00
u_intr_op_done	100.00	100.00	100.00			100.00	100.00
u_kmac_if	97.35	100.00	90.91	100.00	100.00	93.18	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_op_err_alert	100.00			100.00
u_reg	99.53	98.80	99.24	100.00		99.61	100.00
u_reseed_ctrl	98.36	100.00	91.80	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	98.87	100.00	94.34		100.00	100.00	100.00
u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
TOTAL		74	71	95.95
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
ALWAYS	722	5	5	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	780	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
234	1	1
235	1	1
237	1	1
238	1	1
271	2	2
275	1	1
325	1	1
327	1	1
345	1	1
352	1	1
368	1	1
398	1	1
403	1	1
416	1	1
418	1	1
436	1	1
443	1	1
456	1	1
458	1	1
460	1	1
461	1	1
464	1	1
469	1	1
472	0	1
473	0	1
474	0	1
482	1	1
483	1	1
486	1	1
488	1	1
498	1	1
499	1	1
500	1	1
537	1	1
538	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
544	1	1
551	1	1
552	1	1
553	1	1
554	1	1
671	1	1
672	1	1
673	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
712	1	1
714	1	1
717	1	1
718	1	1
722	1	1
723	1	1
724	1	1
726	1	1
727	1	1
732	1	1
749	1	1
780		unreachable

---

Cond Coverage for Module : keymgr

	Total	Covered	Percent
Conditions	186	183	98.39
Logical	186	183	98.39
Non-Logical	0	0
Event	0	0

 LINE       214
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T14
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (seed_en & ((~reg2hw.start.q)))
             ---1---   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       335
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       352
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T14
1	1	Covered	T1,T3,T14

 LINE       368
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (cdi_sel == 1'b0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (cdi_sel == 1'b1)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       443
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T92,T93,T94
1	0	1	1	Covered	T95,T96,T97
1	1	0	1	Covered	T96,T97,T98
1	1	1	0	Covered	T23,T99,T100
1	1	1	1	Covered	T1,T2,T3

 LINE       483
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       488
 EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       537
 EXPRESSION (adv_en | id_en | gen_en)
             ---1--   --2--   ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       538
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T98,T101
1	0	1	Covered	T102,T103,T104
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T98,T101

 LINE       538
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       539
 EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
             ---1--   -----------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T105
1	0	1	Covered	T27,T100,T95
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T22,T105

 LINE       539
 SUB-EXPRESSION (stage_sel == OwnerInt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       540
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
             ---1--   -----------2----------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T95,T96
1	0	1	Covered	T27,T104,T106
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T95,T96

 LINE       540
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       541
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T95,T96,T98
1	0	1	Covered	T27,T102,T97
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T95,T96,T98

 LINE       541
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       542
 EXPRESSION (gen_en & ((~key_version_vld)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T26,T27

 LINE       543
 EXPRESSION (valid_op & ((~key_vld)))
             ----1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       544
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
             ---1--   -----------2----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T100,T95
1	0	1	Covered	T27,T97,T103
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T100,T95

 LINE       544
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       551
 EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T106,T107,T108
1	0	Covered	T1,T2,T3

 LINE       553
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3

 LINE       554
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       631
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T55,T109
1	0	Covered	T1,T2,T3

 LINE       714
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T34,T31

 LINE       714
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       718
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       718
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T112
1	0	Covered	T1,T2,T3
1	1	Covered	T110,T111,T112

 LINE       749
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T112
1	0	Covered	T1,T2,T3
1	1	Covered	T110,T111,T112

---

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	65	97.01
Total Bits	10068	10064	99.96
Total Bits 0->1	5034	5032	99.96
Total Bits 1->0	5034	5032	99.96

Ports	67	65	97.01
Port Bits	10068	10064	99.96
Port Bits 0->1	5034	5032	99.96
Port Bits 1->0	5034	5032	99.96

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T12,T34,T31	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T12,T34,T31	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T12,T34,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T12,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T12,T55,T56	Yes	T12,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.valid	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1:0][383:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
otbn_key_o.valid	Yes	Yes	T1,T14,T17	Yes	T1,T14,T17	OUTPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	Yes	Yes	T35,T24,T36	Yes	T12,T35,T24	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T16,T43,T34	Yes	T1,T13,T14	INPUT
lc_keymgr_div_i[127:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
otp_key_i.owner_seed_valid	Yes	Yes	T31,T4,T113	Yes	T4,T109,T113	INPUT
otp_key_i.owner_seed[255:0]	Yes	Yes	T31,T4,T114	Yes	T4,T114,T36	INPUT
otp_key_i.creator_seed_valid	Yes	Yes	T4,T114,T113	Yes	T4,T114,T36	INPUT
otp_key_i.creator_seed[255:0]	Yes	Yes	T4,T109,T113	Yes	T31,T4,T113	INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T4,T114,T113	Yes	T4,T114,T113	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T114,T109,T113	Yes	T114,T113,T115	INPUT
otp_device_id_i[255:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][4:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][5]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][6]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][7]	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	INPUT
flash_i.seeds[0][8]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][9]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][12:10]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][13]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][14]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[0][20:15]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][21]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][27:22]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][28]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][29]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][30]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][31]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][32]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][35:33]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][36]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][41:37]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][42]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][43]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[0][45:44]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][46]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][47]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][48]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][49]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][51:50]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][52]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][62:53]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][63]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][64]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][76:65]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][77]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][80:78]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][82:81]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[0][83]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][84]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][85]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][86]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][87]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][88]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][96:89]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][97]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[0][100:98]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][101]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][102]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][103]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[0][109:104]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][110]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[0][111]	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	INPUT
flash_i.seeds[0][113:112]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][114]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][115]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][125:116]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][126]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][127]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][128]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][132:129]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][133]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][142:134]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][143]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][144]	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	INPUT
flash_i.seeds[0][145]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][146]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][147]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][148]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][149]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][160:150]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][161]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][162]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][163]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][166:164]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][167]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][172:168]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][173]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][174]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][175]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[0][181:176]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][182]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][184:183]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][185]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][186]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[0][188:187]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][189]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][198:190]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][199]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][201:200]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][202]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][204:203]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][205]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][206]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][207]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][208]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][210:209]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][211]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][212]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][213]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][214]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][217:215]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][218]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][221:219]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][222]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][223]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][236:224]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][237]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][238]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][239]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][241:240]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][242]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][248:243]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][249]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][250]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][251]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[0][255:252]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][1:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][2]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[1][4:3]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][5]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][10:6]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][12:11]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][16:13]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][17]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][18]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][19]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][26:20]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][27]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][39:28]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][40]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][41]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][42]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][49:43]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][50]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][51]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][54:52]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][55]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[1][57:56]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][60:58]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][61]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][64:62]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][65]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][69:66]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][70]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][72:71]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][73]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][74]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[1][76:75]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][77]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][78]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][81:79]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][82]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][86:83]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][87]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][91:88]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][92]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][94:93]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][95]	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	INPUT
flash_i.seeds[1][99:96]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][100]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][102:101]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][103]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][105:104]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][106]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][110:107]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][111]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][122:112]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][123]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][125:124]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][126]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][127]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][128]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][129]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[1][130]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][134:131]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][135]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][136]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][142:137]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][143]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][145:144]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][146]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][147]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][150:148]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][152:151]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[1][156:153]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][158:157]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][159]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][160]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][161]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][162]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][163]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[1][166:164]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][167]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][168]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][169]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][170]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][171]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][172]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][178:173]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][179]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][183:180]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][184]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][191:185]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][192]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][199:193]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][200]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][210:201]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][211]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][212]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][214:213]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][215]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][216]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][217]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][218]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][219]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][223:220]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][224]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][225]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][226]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][232:227]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][233]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[1][234]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][238:235]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][239]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[1][240]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][244:241]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][245]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][246]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][247]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][248]	Yes	Yes	T1,T14,T16	Yes	T1,T14,T16	INPUT
flash_i.seeds[1][249]	Yes	Yes	T3,T14,T16	Yes	T3,T14,T16	INPUT
flash_i.seeds[1][250]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][251]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][252]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
flash_i.seeds[1][255:253]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T14	INPUT
edn_i.edn_fips	Yes	Yes	T2,T3,T14	Yes	T1,T2,T3	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.valid	Yes	Yes	T23,T99,T100	Yes	T23,T99,T95	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
intr_op_done_o	Yes	Yes	T2,T12,T15	Yes	T2,T12,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T12,T34,T31	Yes	T12,T34,T31	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T12,T34,T31	Yes	T12,T34,T31	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
TERNARY	398	3	2	66.67
TERNARY	483	4	4	100.00
TERNARY	488	2	2	100.00
TERNARY	714	3	2	66.67
TERNARY	718	3	3	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	631	2	2	100.00
IF	722	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	398	((cdi_sel == 1'b0)) ? 
-2-:	398	((cdi_sel == 1'b1)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	483	((dest_sel == Aes)) ? 
-2-:	483	((dest_sel == Kmac)) ? 
-3-:	483	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	(invalid_stage_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	714	(fault_errs) ? 
-2-:	714	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T34,T31
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	(op_errs) ? 
-2-:	718	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	722	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	869	869	0	0
AesKeyKnownO_A	25097741	24925688	0	0
AlertKnownO_A	25097741	24925688	0	0
ErrCntMatch_A	869	869	0	0
FaultCntMatch_A	869	869	0	0
FpvSecCmCtrlCntAlertCheck_A	25097741	90	0	0
FpvSecCmCtrlDataFsmCheck_A	25097741	90	0	0
FpvSecCmCtrlMainFsmCheck_A	25097741	90	0	0
FpvSecCmCtrlOpFsmCheck_A	25097741	90	0	0
FpvSecCmKmacIfCntAlertCheck_A	25097741	90	0	0
FpvSecCmKmacIfFsmCheck_A	25097741	90	0	0
FpvSecCmRegWeOnehotCheck_A	25097741	90	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	25097741	90	0	0
FpvSecCmSideloadCtrlFsmCheck_A	25097741	90	0	0
GenDataWidth_A	869	869	0	0
IdDataWidth_A	869	869	0	0
IntrKnownO_A	25097741	24925688	0	0
KmacDataKnownO_A	24235540	24067262	0	0
KmacKeyKnownO_A	25097741	24925688	0	0
KmacMaskCheck_A	869	869	0	0
LfsrWidth_A	869	869	0	0
OtbnKeyKnownO_A	25097741	24925688	0	0
OutputKeyDiff_A	869	869	0	0
StageMatch_A	869	869	0	0
TlAReadyKnownO_A	25097741	24925688	0	0
TlDValidKnownO_A	25097741	24925688	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	90	0	0
T6	38792	20	0	0
T10	0	10	0	0
T11	0	20	0	0
T19	6448	0	0	0
T41	0	20	0	0
T59	11102	0	0	0
T60	18978	0	0	0
T116	0	20	0	0
T117	3777	0	0	0
T118	3115	0	0	0
T119	2027	0	0	0
T120	7374	0	0	0
T121	93898	0	0	0
T122	14487	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

IdDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24235540	24067262	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

StageMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869	869	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25097741	24925688	0	0
T1	6207	6122	0	0
T2	79054	78960	0	0
T3	122821	122738	0	0
T12	10760	10593	0	0
T13	4473	4398	0	0
T14	3472	3415	0	0
T15	14011	13944	0	0
T16	8096	8007	0	0
T17	6602	6542	0	0
T18	4247	4168	0	0