d0c52cdadd
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 50.270s | 5.920ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 47.230s | 4.612ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.490s | 37.811us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 16.400s | 882.177us | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 11.200s | 2.040ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.620s | 287.024us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 11.200s | 2.040ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.206m | 9.567ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 1.076m | 3.646ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.257m | 7.657ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.244m | 6.580ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 59.530s | 1.875ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 38.130s | 5.980ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 38.470s | 2.873ms | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 12.380s | 2.342ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 51.110s | 3.722ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 39.290s | 6.648ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 22.480s | 2.278ms | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 7.241m | 18.692ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.960s | 57.307us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 0.950s | 30.501us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.710s | 3.023ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.710s | 3.023ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.490s | 37.811us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.200s | 2.040ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.870s | 217.271us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.490s | 37.811us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.200s | 2.040ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.870s | 217.271us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 737 | 740 | 99.59 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 8.240s | 791.039us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.160s | 598.732us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.160s | 598.732us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.160s | 598.732us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.160s | 598.732us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 14.560s | 1.002ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 8.240s | 791.039us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.160s | 598.732us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.206m | 9.567ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 47.230s | 4.612ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 47.230s | 4.612ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 47.230s | 4.612ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.580s | 54.323us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 38.470s | 2.873ms | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 39.290s | 6.648ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 39.290s | 6.648ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 47.230s | 4.612ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 27.990s | 898.801us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 19.140s | 936.266us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 38.470s | 2.873ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 19.140s | 936.266us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 19.140s | 936.266us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 19.140s | 936.266us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.010s | 654.549us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 19.140s | 936.266us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 28.420s | 1.505ms | 33 | 50 | 66.00 |
V3 | TOTAL | 33 | 50 | 66.00 | |||
TOTAL | 1090 | 1110 | 98.20 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.73 | 99.03 | 98.15 | 98.37 | 100.00 | 99.02 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 17 failures:
11.keymgr_stress_all_with_rand_reset.24080748223382993073986951464488413429889955920354873545321507341454041811084
Line 564, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 158381702 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 158381702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.keymgr_stress_all_with_rand_reset.114551493800667537109611150187118809281297503858413532926515403252588134292824
Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 229305842 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 229305842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_sync_async_fault_cross has 1 failures.
3.keymgr_sync_async_fault_cross.89507136796296193117026615424628580522325108352462988717302545646471426740465
Line 288, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 19763966 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 19763966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
47.keymgr_stress_all.79895587392505061186311852224358724400673347356784531048958159916196281773234
Line 1629, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log
UVM_ERROR @ 593401632 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 593401632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
21.keymgr_lc_disable.78236863902634233241432247060244827963667176799626956255193297470391733445950
Line 289, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 57431423 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
UVM_INFO @ 57431423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---