Line Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
TOTAL | | 75 | 72 | 96.00 |
CONT_ASSIGN | 210 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 463 | 1 | 1 | 100.00 |
CONT_ASSIGN | 468 | 1 | 1 | 100.00 |
CONT_ASSIGN | 471 | 1 | 0 | 0.00 |
CONT_ASSIGN | 472 | 1 | 0 | 0.00 |
CONT_ASSIGN | 473 | 1 | 0 | 0.00 |
CONT_ASSIGN | 481 | 1 | 1 | 100.00 |
CONT_ASSIGN | 482 | 1 | 1 | 100.00 |
CONT_ASSIGN | 485 | 1 | 1 | 100.00 |
CONT_ASSIGN | 487 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 538 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
CONT_ASSIGN | 541 | 1 | 1 | 100.00 |
CONT_ASSIGN | 542 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
CONT_ASSIGN | 552 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
CONT_ASSIGN | 670 | 1 | 1 | 100.00 |
CONT_ASSIGN | 671 | 1 | 1 | 100.00 |
CONT_ASSIGN | 672 | 1 | 1 | 100.00 |
CONT_ASSIGN | 674 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 677 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 681 | 1 | 1 | 100.00 |
CONT_ASSIGN | 682 | 1 | 1 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
CONT_ASSIGN | 686 | 1 | 1 | 100.00 |
CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
CONT_ASSIGN | 711 | 1 | 1 | 100.00 |
CONT_ASSIGN | 713 | 1 | 1 | 100.00 |
CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
ALWAYS | 721 | 5 | 5 | 100.00 |
CONT_ASSIGN | 731 | 1 | 1 | 100.00 |
CONT_ASSIGN | 748 | 1 | 1 | 100.00 |
CONT_ASSIGN | 779 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
210 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
271 |
2 |
2 |
275 |
1 |
1 |
326 |
1 |
1 |
328 |
1 |
1 |
346 |
1 |
1 |
353 |
1 |
1 |
369 |
1 |
1 |
399 |
1 |
1 |
404 |
1 |
1 |
417 |
1 |
1 |
419 |
1 |
1 |
436 |
1 |
1 |
442 |
1 |
1 |
455 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
463 |
1 |
1 |
468 |
1 |
1 |
471 |
0 |
1 |
472 |
0 |
1 |
473 |
0 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
485 |
1 |
1 |
487 |
1 |
1 |
497 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
536 |
1 |
1 |
537 |
1 |
1 |
538 |
1 |
1 |
539 |
1 |
1 |
540 |
1 |
1 |
541 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
550 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
553 |
1 |
1 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
678 |
1 |
1 |
679 |
1 |
1 |
680 |
1 |
1 |
681 |
1 |
1 |
682 |
1 |
1 |
683 |
1 |
1 |
684 |
1 |
1 |
685 |
1 |
1 |
686 |
1 |
1 |
687 |
1 |
1 |
711 |
1 |
1 |
713 |
1 |
1 |
716 |
1 |
1 |
717 |
1 |
1 |
721 |
1 |
1 |
722 |
1 |
1 |
723 |
1 |
1 |
725 |
1 |
1 |
726 |
1 |
1 |
731 |
1 |
1 |
748 |
1 |
1 |
779 |
|
unreachable |
Cond Coverage for Module :
keymgr
| Total | Covered | Percent |
Conditions | 183 | 180 | 98.36 |
Logical | 183 | 180 | 98.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 210
EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
------1----- ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T13 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 336
EXPRESSION (op_start & op_done)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 353
EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
-------------1------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T13,T15,T16 |
LINE 369
EXPRESSION (sw_binding_regwen & cfg_regwen)
--------1-------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b1)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
--------1------- ----2---- --------3------- -------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T87,T88,T89 |
1 | 0 | 1 | 1 | Covered | T90,T87,T91 |
1 | 1 | 0 | 1 | Covered | T13,T90,T87 |
1 | 1 | 1 | 0 | Covered | T13,T15,T45 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 482
EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 482
SUB-EXPRESSION (dest_sel == Aes)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 482
SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 482
SUB-EXPRESSION (dest_sel == Kmac)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 482
SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (dest_sel == Otbn)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 487
EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 536
EXPRESSION (adv_en | id_en | gen_en)
---1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T3,T4 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 537
EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T89,T92,T93 |
1 | 0 | 1 | Covered | T24,T89,T94 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T92,T93 |
LINE 537
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 538
EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
---1-- -----------2----------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T24,T95,T21 |
1 | 0 | 1 | Covered | T24,T95,T96 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T21,T97,T98 |
LINE 538
SUB-EXPRESSION (stage_sel == OwnerInt)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 539
EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
---1-- -----------2---------- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T21,T99,T94 |
1 | 0 | 1 | Covered | T24,T25,T21 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T99,T100,T101 |
LINE 539
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 540
EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T25,T21,T99 |
1 | 0 | 1 | Covered | T21,T102,T99 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T25,T96,T100 |
LINE 540
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 541
EXPRESSION (gen_en & ((~key_version_vld)))
---1-- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T16,T18,T27 |
LINE 542
EXPRESSION (valid_op & ((~key_vld)))
----1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T22,T23,T26 |
LINE 543
EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
---1-- -----------2---------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T24,T25,T103 |
1 | 0 | 1 | Covered | T24,T25,T21 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T24,T25,T103 |
LINE 543
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 550
EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T24,T95,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 552
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 553
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T34,T50,T53 |
1 | 0 | Covered | T1,T2,T3 |
LINE 713
EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T14,T34 |
LINE 713
SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 717
EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 717
SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 731
EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T104,T82,T105 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T104,T82,T105 |
LINE 748
EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T104,T82,T105 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T104,T82,T105 |
Toggle Coverage for Module :
keymgr
| Total | Covered | Percent |
Totals |
67 |
65 |
97.01 |
Total Bits |
10068 |
10064 |
99.96 |
Total Bits 0->1 |
5034 |
5032 |
99.96 |
Total Bits 1->0 |
5034 |
5032 |
99.96 |
| | | |
Ports |
67 |
65 |
97.01 |
Port Bits |
10068 |
10064 |
99.96 |
Port Bits 0->1 |
5034 |
5032 |
99.96 |
Port Bits 1->0 |
5034 |
5032 |
99.96 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T13,T14 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T1,T13,T14 |
Yes |
T1,T2,T3 |
INPUT |
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_edn_ni |
Yes |
Yes |
T1,T13,T14 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T15,T17,T33 |
Yes |
T15,T17,T33 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T3,T13 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T1,T14,T33 |
Yes |
T1,T14,T33 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T3,T13 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][5:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][6] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][9:7] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][11:10] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][21:12] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][22] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][37:23] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][38] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][41:39] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][43:42] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][53:44] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][54] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][69:55] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][70] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][73:71] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][75:74] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][85:76] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][86] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][101:87] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][102] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][105:103] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][107:106] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][117:108] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][118] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][133:119] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][134] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][137:135] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][139:138] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][149:140] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][150] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][165:151] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][166] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][169:167] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][171:170] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][181:172] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][182] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][197:183] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][198] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][201:199] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][203:202] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][213:204] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][214] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][229:215] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][230] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][233:231] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][235:234] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][245:236] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[0][246] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[0][255:247] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][10:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][11] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][12] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][13] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][15:14] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][16] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][22:17] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][24:23] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][26:25] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][27] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][29:28] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][30] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][42:31] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][43] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][44] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][45] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][47:46] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][48] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][54:49] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][56:55] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][58:57] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][59] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][61:60] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][62] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][74:63] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][75] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][76] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][77] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][79:78] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][80] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][86:81] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][88:87] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][90:89] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][91] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][93:92] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][94] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][106:95] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][107] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][108] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][109] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][111:110] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][112] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][118:113] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][120:119] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][122:121] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][123] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][125:124] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][126] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][138:127] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][139] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][140] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][141] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][143:142] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][144] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][150:145] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][152:151] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][154:153] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][155] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][157:156] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][158] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][170:159] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][171] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][172] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][173] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][175:174] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][176] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][182:177] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][184:183] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][186:185] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][187] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][189:188] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][190] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][202:191] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][203] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][204] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][205] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][207:206] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][208] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][214:209] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][216:215] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][218:217] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][219] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][221:220] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][222] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][234:223] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][235] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][236] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][237] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][239:238] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][240] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][246:241] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][248:247] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][250:249] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][251] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][253:252] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.key[1][254] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
aes_key_o.key[1][255] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
aes_key_o.valid |
Yes |
Yes |
T14,T16,T33 |
Yes |
T14,T16,T18 |
OUTPUT |
kmac_key_o.key[1:0][255:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_key_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][5:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][6] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][9:7] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][11:10] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][21:12] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][22] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][37:23] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][38] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][41:39] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][43:42] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][53:44] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][54] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][69:55] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][70] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][73:71] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][75:74] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][85:76] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][86] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][101:87] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][102] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][105:103] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][107:106] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][117:108] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][118] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][133:119] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][134] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][137:135] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][139:138] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][149:140] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][150] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][165:151] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][166] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][169:167] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][171:170] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][181:172] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][182] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][197:183] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][198] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][201:199] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][203:202] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][213:204] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][214] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][229:215] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][230] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][233:231] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][235:234] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][245:236] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][246] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][261:247] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][262] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][265:263] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][267:266] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][277:268] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][278] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][293:279] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][294] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][297:295] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][299:298] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][309:300] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][310] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][325:311] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][326] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][329:327] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][331:330] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][341:332] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][342] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][357:343] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][358] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][361:359] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][363:362] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][373:364] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[0][374] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[0][383:375] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][10:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][11] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][12] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][13] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][15:14] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][16] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][22:17] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][24:23] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][26:25] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][27] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][29:28] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][30] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][42:31] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][43] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][44] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][45] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][47:46] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][48] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][54:49] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][56:55] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][58:57] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][59] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][61:60] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][62] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][74:63] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][75] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][76] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][77] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][79:78] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][80] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][86:81] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][88:87] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][90:89] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][91] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][93:92] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][94] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][106:95] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][107] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][108] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][109] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][111:110] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][112] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][118:113] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][120:119] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][122:121] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][123] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][125:124] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][126] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][138:127] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][139] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][140] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][141] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][143:142] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][144] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][150:145] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][152:151] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][154:153] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][155] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][157:156] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][158] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][170:159] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][171] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][172] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][173] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][175:174] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][176] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][182:177] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][184:183] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][186:185] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][187] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][189:188] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][190] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][202:191] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][203] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][204] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][205] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][207:206] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][208] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][214:209] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][216:215] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][218:217] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][219] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][221:220] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][222] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][234:223] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][235] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][236] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][237] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][239:238] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][240] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][246:241] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][248:247] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][250:249] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][251] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][253:252] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][254] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][266:255] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][267] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][268] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][269] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][271:270] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][272] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][278:273] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][280:279] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][282:281] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][283] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][285:284] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][286] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][298:287] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][299] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][300] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][301] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][303:302] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][304] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][310:305] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][312:311] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][314:313] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][315] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][317:316] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][318] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][330:319] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][331] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][332] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][333] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][335:334] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][336] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][342:337] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][344:343] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][346:345] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][347] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][349:348] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][350] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][362:351] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][363] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][364] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][365] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][367:366] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][368] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][374:369] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][376:375] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][378:377] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][379] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][381:380] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.key[1][382] |
Yes |
Yes |
T2,T13,T4 |
Yes |
T2,T13,T4 |
OUTPUT |
otbn_key_o.key[1][383] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
otbn_key_o.valid |
Yes |
Yes |
T2,T4,T18 |
Yes |
T2,T4,T18 |
OUTPUT |
kmac_data_o.last |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.strb[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.data[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_i.error |
Yes |
Yes |
T19,T29,T38 |
Yes |
T1,T14,T19 |
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_en_masking_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_keymgr_en_i[3:0] |
Yes |
Yes |
T13,T14,T33 |
Yes |
T1,T3,T13 |
INPUT |
lc_keymgr_div_i[127:0] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
otp_key_i.owner_seed_valid |
Yes |
Yes |
T33,T42,T50 |
Yes |
T33,T51,T42 |
INPUT |
otp_key_i.owner_seed[255:0] |
Yes |
Yes |
T33,T51,T50 |
Yes |
T13,T33,T50 |
INPUT |
otp_key_i.creator_seed_valid |
Yes |
Yes |
T33,T42,T50 |
Yes |
T33,T42,T50 |
INPUT |
otp_key_i.creator_seed[255:0] |
Yes |
Yes |
T5,T106,T53 |
Yes |
T5,T106,T53 |
INPUT |
otp_key_i.creator_root_key_share1_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share1[255:0] |
Yes |
Yes |
T42,T50,T5 |
Yes |
T42,T50,T5 |
INPUT |
otp_key_i.creator_root_key_share0_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share0[255:0] |
Yes |
Yes |
T33,T51,T42 |
Yes |
T33,T42,T50 |
INPUT |
otp_device_id_i[255:0] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][1:0] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][2] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][4:3] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][5] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][8:6] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][9] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][10] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][11] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][12] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][13] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][14] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][15] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][22:16] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][23] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][27:24] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][28] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][29] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[0][34:30] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][35] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][36] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][37] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][44:38] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][45] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[0][48:46] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][49] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][50] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][51] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][52] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][53] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][57:54] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][58] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][63:59] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][64] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][67:65] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][68] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][74:69] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][76:75] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][78:77] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][79] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][80] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][81] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][82] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[0][84:83] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][85] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][86] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[0][87] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][88] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][89] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][90] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][91] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][92] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][99:93] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][100] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][106:101] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][107] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][110:108] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][111] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][112] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][113] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][118:114] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][119] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][120] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[0][123:121] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][124] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][125] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][126] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][127] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][128] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][131:129] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][132] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][136:133] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][138:137] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][143:139] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][144] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][145] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][146] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][148:147] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][149] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][150] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][151] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][153:152] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][154] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][155] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][158:156] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][159] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][168:160] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][169] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][170] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][171] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][172] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][175:173] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][176] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][177] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][178] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][184:179] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][185] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][190:186] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][191] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][192] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][193] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][197:194] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][198] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][199] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][201:200] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][202] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][203] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][205:204] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][206] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[0][208:207] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][209] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][210] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][212:211] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][213] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][216:214] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][218:217] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][219] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][220] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][221] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][222] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][227:223] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][228] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][230:229] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][231] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][232] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][233] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][238:234] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][239] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][240] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][241] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][248:242] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][249] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][250] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][251] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][252] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][253] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[0][255:254] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][0] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][1] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][5:2] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][6] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][7] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][8] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][9] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][10] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][11] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][12] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][13] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][14] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][16:15] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][17] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][18] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][19] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][20] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][21] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][23:22] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][25:24] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][26] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][28:27] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][30:29] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][31] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][35:32] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][36] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][37] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][38] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][39] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][40] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[1][41] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][47:42] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][48] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][51:49] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][52] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][53] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][54] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][57:55] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][58] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][59] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][60] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][62:61] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][63] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][64] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][65] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][68:66] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][69] |
Yes |
Yes |
T15,T16,T18 |
Yes |
T15,T16,T18 |
INPUT |
flash_i.seeds[1][70] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][73:71] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][74] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][75] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][76] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][78:77] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][79] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][86:80] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][87] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][88] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][91:89] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][92] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][95:93] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][96] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][100:97] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][101] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][102] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][103] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][105:104] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][106] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][107] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][108] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][110:109] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][111] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][113:112] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][114] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][116:115] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][117] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][122:118] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][123] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][124] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][125] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][127:126] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][129:128] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][130] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][131] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][132] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][133] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][136:134] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][137] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][139:138] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][140] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][142:141] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][143] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][144] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[1][147:145] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][148] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[1][152:149] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][153] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][158:154] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][159] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[1][161:160] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][162] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][163] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][164] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][170:165] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][171] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][172] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][173] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][176:174] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][177] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][178] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][180:179] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][181] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][182] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][183] |
Yes |
Yes |
T13,T15,T18 |
Yes |
T13,T15,T18 |
INPUT |
flash_i.seeds[1][184] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][185] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][186] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][187] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][191:188] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][192] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][198:193] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][199] |
Yes |
Yes |
T13,T16,T27 |
Yes |
T13,T16,T27 |
INPUT |
flash_i.seeds[1][202:200] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][203] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][204] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][211:205] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][212] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][213] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][214] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][216:215] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][217] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][220:218] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][221] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][222] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][226:223] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][227] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][228] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][229] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][231:230] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][232] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][240:233] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][241] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][243:242] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][244] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][245] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][246] |
Yes |
Yes |
T13,T16,T18 |
Yes |
T13,T16,T18 |
INPUT |
flash_i.seeds[1][249:247] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][251:250] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][253:252] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][254] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
flash_i.seeds[1][255] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T16 |
INPUT |
edn_o.edn_req |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
edn_i.edn_bus[31:0] |
Yes |
Yes |
T2,T3,T14 |
Yes |
T2,T3,T14 |
INPUT |
edn_i.edn_fips |
Yes |
Yes |
T1,T2,T3 |
Yes |
T2,T3,T14 |
INPUT |
edn_i.edn_ack |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_digest_i.valid |
Yes |
Yes |
T15,T45,T38 |
Yes |
T15,T45,T38 |
INPUT |
rom_digest_i.data[255:0] |
Yes |
Yes |
T13,T15,T16 |
Yes |
T13,T15,T18 |
INPUT |
intr_op_done_o |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T1,T14,T34 |
Yes |
T1,T14,T34 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T1,T14,T34 |
Yes |
T1,T14,T34 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
Branches |
|
49 |
47 |
95.92 |
TERNARY |
399 |
3 |
2 |
66.67 |
TERNARY |
482 |
4 |
4 |
100.00 |
TERNARY |
487 |
2 |
2 |
100.00 |
TERNARY |
713 |
3 |
2 |
66.67 |
TERNARY |
717 |
3 |
3 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
IF |
721 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 399 ((cdi_sel == 1'b0)) ?
-2-: 399 ((cdi_sel == 1'b1)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 482 ((dest_sel == Aes)) ?
-2-: 482 ((dest_sel == Kmac)) ?
-3-: 482 ((dest_sel == Otbn)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T3,T13 |
0 |
1 |
- |
Covered |
T1,T3,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 487 (invalid_stage_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 713 (fault_errs) ?
-2-: 713 (fault_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T14,T34 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 717 (op_errs) ?
-2-: 717 (op_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 721 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
keymgr
Assertion Details
AdvDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
AesKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
ErrCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FaultCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FpvSecCmCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmCtrlDataFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmCtrlMainFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmCtrlOpFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmKmacIfCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmKmacIfFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmReseedCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
FpvSecCmSideloadCtrlFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
80 |
0 |
0 |
T5 |
234907 |
0 |
0 |
0 |
T10 |
51937 |
20 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T29 |
12308 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
20 |
0 |
0 |
T43 |
8088 |
0 |
0 |
0 |
T50 |
30326 |
0 |
0 |
0 |
T63 |
21463 |
0 |
0 |
0 |
T107 |
5883 |
0 |
0 |
0 |
T108 |
4631 |
0 |
0 |
0 |
T109 |
1859 |
0 |
0 |
0 |
T110 |
55579 |
0 |
0 |
0 |
GenDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IdDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IntrKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
KmacDataKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18731364 |
18595036 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
KmacKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
KmacMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
LfsrWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OtbnKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
OutputKeyDiff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
StageMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
880 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |