Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3268492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

650042

1

T1

207

T2

158

T3

376

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3473438	1			T1	665		T2	1191		T3	1001
values[0x0]	220400	1			T1	65		T2	40		T3	138
values[0x1]	224696	1			T1	59		T2	38		T3	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2240364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1678170

1

T1

367

T2

504

T3

641

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22670	1			T2	3		T3	9		T4	5
valid_sources[0x01]	14051	1			T2	9		T3	5		T17	20
valid_sources[0x02]	17224	1			T3	4		T14	12		T17	6
valid_sources[0x03]	13736	1			T3	8		T14	7		T18	9
valid_sources[0x04]	15120	1			T2	1		T3	9		T14	8
valid_sources[0x05]	35003	1			T2	9		T3	6		T4	2
valid_sources[0x06]	13470	1			T2	1		T3	4		T4	2
valid_sources[0x07]	13463	1			T3	5		T4	1		T14	2
valid_sources[0x08]	18118	1			T2	12		T3	2		T4	3
valid_sources[0x09]	14715	1			T2	1		T3	8		T4	2
valid_sources[0x0a]	27186	1			T2	1		T3	2		T4	1
valid_sources[0x0b]	13610	1			T2	1		T3	3		T14	2
valid_sources[0x0c]	15520	1			T2	8		T3	5		T4	2
valid_sources[0x0d]	14519	1			T2	2		T3	4		T4	1
valid_sources[0x0e]	13055	1			T2	1		T3	8		T4	2
valid_sources[0x0f]	15055	1			T2	2		T3	10		T18	7
valid_sources[0x10]	17158	1			T2	5		T3	5		T4	1
valid_sources[0x11]	15831	1			T2	2		T3	5		T4	2
valid_sources[0x12]	13332	1			T2	1		T3	9		T4	1
valid_sources[0x13]	14524	1			T3	3		T4	1		T18	4
valid_sources[0x14]	14781	1			T2	10		T3	9		T4	2
valid_sources[0x15]	14057	1			T2	2		T3	4		T4	1
valid_sources[0x16]	13122	1			T2	1		T3	8		T4	1
valid_sources[0x17]	13839	1			T2	11		T3	4		T14	2
valid_sources[0x18]	14262	1			T2	6		T3	5		T4	2
valid_sources[0x19]	13058	1			T2	8		T4	3		T14	9
valid_sources[0x1a]	13300	1			T2	8		T3	7		T4	1
valid_sources[0x1b]	16535	1			T2	15		T3	2		T4	3
valid_sources[0x1c]	15032	1			T2	16		T3	4		T4	2
valid_sources[0x1d]	15322	1			T2	4		T3	7		T4	2
valid_sources[0x1e]	23641	1			T2	6		T3	5		T4	6
valid_sources[0x1f]	13167	1			T2	16		T3	6		T4	2
valid_sources[0x20]	14165	1			T2	5		T3	6		T4	4
valid_sources[0x21]	13220	1			T3	6		T4	1		T14	5
valid_sources[0x22]	14303	1			T2	9		T3	7		T14	8
valid_sources[0x23]	13795	1			T2	2		T3	6		T4	2
valid_sources[0x24]	52495	1			T2	14		T3	4		T4	1
valid_sources[0x25]	14166	1			T2	5		T3	6		T4	1
valid_sources[0x26]	13729	1			T3	5		T4	2		T14	8
valid_sources[0x27]	13366	1			T3	4		T14	3		T16	7
valid_sources[0x28]	14955	1			T3	7		T4	2		T14	2
valid_sources[0x29]	13680	1			T2	5		T3	5		T18	4
valid_sources[0x2a]	14466	1			T2	2		T3	4		T4	2
valid_sources[0x2b]	15503	1			T2	11		T3	4		T14	2
valid_sources[0x2c]	13817	1			T2	3		T3	4		T14	14
valid_sources[0x2d]	14741	1			T3	2		T4	2		T14	23
valid_sources[0x2e]	12901	1			T3	4		T14	12		T16	15
valid_sources[0x2f]	13138	1			T2	4		T3	3		T4	3
valid_sources[0x30]	15262	1			T3	6		T4	5		T14	2
valid_sources[0x31]	15235	1			T3	6		T16	22		T18	7
valid_sources[0x32]	12849	1			T2	4		T3	5		T4	1
valid_sources[0x33]	13177	1			T2	1		T3	4		T4	1
valid_sources[0x34]	17664	1			T2	1		T3	4		T4	1
valid_sources[0x35]	13965	1			T2	5		T3	6		T14	13
valid_sources[0x36]	14147	1			T2	1		T3	6		T14	32
valid_sources[0x37]	14199	1			T2	3		T3	7		T4	2
valid_sources[0x38]	23719	1			T2	1		T3	3		T4	1
valid_sources[0x39]	15257	1			T2	3		T3	8		T4	6
valid_sources[0x3a]	13331	1			T3	6		T16	2		T18	4
valid_sources[0x3b]	13525	1			T2	8		T3	1		T4	2
valid_sources[0x3c]	21633	1			T3	5		T14	1		T16	3
valid_sources[0x3d]	13273	1			T2	6		T3	2		T4	1
valid_sources[0x3e]	13058	1			T3	4		T14	1		T18	2
valid_sources[0x3f]	18375	1			T3	2		T4	1		T18	4
valid_sources[0x40]	12904	1			T2	3		T3	4		T4	2
valid_sources[0x41]	22031	1			T2	2		T3	6		T14	8
valid_sources[0x42]	15663	1			T2	10		T3	8		T14	19
valid_sources[0x43]	14226	1			T2	13		T3	7		T4	2
valid_sources[0x44]	13035	1			T2	2		T3	8		T4	1
valid_sources[0x45]	14937	1			T2	17		T3	6		T14	20
valid_sources[0x46]	13618	1			T2	11		T3	2		T4	5
valid_sources[0x47]	13526	1			T2	1		T3	4		T4	1
valid_sources[0x48]	15114	1			T2	1		T3	5		T14	16
valid_sources[0x49]	15636	1			T2	8		T3	7		T4	2
valid_sources[0x4a]	16767	1			T2	1		T3	4		T4	2
valid_sources[0x4b]	14552	1			T2	11		T3	12		T14	3
valid_sources[0x4c]	14323	1			T2	13		T3	5		T16	3
valid_sources[0x4d]	14161	1			T3	2		T14	15		T18	3
valid_sources[0x4e]	13056	1			T2	6		T3	5		T4	7
valid_sources[0x4f]	26577	1			T3	9		T16	12		T18	6
valid_sources[0x50]	14548	1			T2	1		T3	3		T4	3
valid_sources[0x51]	14365	1			T2	1		T3	5		T14	5
valid_sources[0x52]	13418	1			T2	5		T3	8		T4	2
valid_sources[0x53]	14853	1			T2	9		T3	5		T4	1
valid_sources[0x54]	13959	1			T2	1		T3	6		T4	2
valid_sources[0x55]	13268	1			T3	9		T4	2		T14	3
valid_sources[0x56]	13296	1			T2	3		T3	4		T4	2
valid_sources[0x57]	13146	1			T2	4		T3	4		T4	2
valid_sources[0x58]	13137	1			T2	8		T3	5		T18	6
valid_sources[0x59]	13377	1			T3	4		T4	2		T14	6
valid_sources[0x5a]	13859	1			T2	5		T3	3		T14	7
valid_sources[0x5b]	15168	1			T2	3		T3	3		T4	4
valid_sources[0x5c]	13465	1			T2	7		T3	5		T4	1
valid_sources[0x5d]	13221	1			T2	2		T3	4		T14	9
valid_sources[0x5e]	13890	1			T2	1		T3	2		T4	4
valid_sources[0x5f]	14220	1			T2	5		T3	7		T4	1
valid_sources[0x60]	14234	1			T3	4		T14	8		T17	7
valid_sources[0x61]	14493	1			T2	7		T3	1		T4	1
valid_sources[0x62]	13080	1			T2	11		T3	8		T14	16
valid_sources[0x63]	16959	1			T3	4		T14	3		T16	2
valid_sources[0x64]	15118	1			T2	3		T3	9		T4	1
valid_sources[0x65]	13655	1			T2	8		T3	4		T4	3
valid_sources[0x66]	13586	1			T2	3		T3	1		T14	8
valid_sources[0x67]	13455	1			T2	7		T3	6		T4	1
valid_sources[0x68]	13193	1			T2	2		T3	4		T4	3
valid_sources[0x69]	13653	1			T2	8		T3	3		T4	1
valid_sources[0x6a]	20210	1			T2	11		T3	4		T4	1
valid_sources[0x6b]	13104	1			T2	9		T3	5		T4	1
valid_sources[0x6c]	15284	1			T2	6		T3	9		T14	5
valid_sources[0x6d]	12967	1			T2	1		T3	4		T4	1
valid_sources[0x6e]	12957	1			T2	1		T3	3		T4	1
valid_sources[0x6f]	13507	1			T3	5		T4	2		T14	11
valid_sources[0x70]	13942	1			T2	12		T3	5		T14	4
valid_sources[0x71]	15771	1			T2	3		T3	5		T4	3
valid_sources[0x72]	12849	1			T2	2		T3	5		T14	13
valid_sources[0x73]	17232	1			T2	1		T3	5		T4	2
valid_sources[0x74]	13137	1			T2	6		T3	8		T4	3
valid_sources[0x75]	14252	1			T2	4		T3	3		T14	4
valid_sources[0x76]	13972	1			T2	7		T3	2		T4	7
valid_sources[0x77]	13578	1			T3	3		T14	9		T17	5
valid_sources[0x78]	13420	1			T2	6		T3	1		T4	3
valid_sources[0x79]	14623	1			T2	10		T3	5		T14	1
valid_sources[0x7a]	12840	1			T2	11		T3	3		T14	2
valid_sources[0x7b]	14313	1			T2	3		T3	6		T4	3
valid_sources[0x7c]	14636	1			T2	6		T3	7		T4	1
valid_sources[0x7d]	12944	1			T2	8		T3	4		T14	2
valid_sources[0x7e]	13428	1			T2	6		T3	7		T17	4
valid_sources[0x7f]	13212	1			T3	7		T14	22		T18	7
valid_sources[0x80]	13968	1			T2	4		T3	6		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345765

1

T1

172

T2

133

T3

181

values[0x0]

all_enables

biggest_size

159734

1

T1

23

T2

15

T3

96

values[0x1]

all_enables

biggest_size

144543

1

T1

12

T2

10

T3

99