Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27247890	20833	0	0
attest_sw_binding_0_rd_A	27247890	3162	0	0
attest_sw_binding_1_rd_A	27247890	3316	0	0
attest_sw_binding_2_rd_A	27247890	3230	0	0
attest_sw_binding_3_rd_A	27247890	3175	0	0
attest_sw_binding_4_rd_A	27247890	3155	0	0
attest_sw_binding_5_rd_A	27247890	3209	0	0
attest_sw_binding_6_rd_A	27247890	3170	0	0
attest_sw_binding_7_rd_A	27247890	3222	0	0
intr_enable_rd_A	27247890	4075	0	0
key_version_rd_A	27247890	3133	0	0
max_creator_key_ver_regwen_rd_A	27247890	3130	0	0
max_owner_int_key_ver_regwen_rd_A	27247890	3109	0	0
max_owner_key_ver_regwen_rd_A	27247890	3136	0	0
reseed_interval_regwen_rd_A	27247890	3333	0	0
salt_0_rd_A	27247890	3272	0	0
salt_1_rd_A	27247890	3053	0	0
salt_2_rd_A	27247890	3141	0	0
salt_3_rd_A	27247890	3228	0	0
salt_4_rd_A	27247890	3117	0	0
salt_5_rd_A	27247890	3277	0	0
salt_6_rd_A	27247890	3222	0	0
salt_7_rd_A	27247890	3192	0	0
sealing_sw_binding_0_rd_A	27247890	3128	0	0
sealing_sw_binding_1_rd_A	27247890	3324	0	0
sealing_sw_binding_2_rd_A	27247890	3147	0	0
sealing_sw_binding_3_rd_A	27247890	3090	0	0
sealing_sw_binding_4_rd_A	27247890	3137	0	0
sealing_sw_binding_5_rd_A	27247890	3201	0	0
sealing_sw_binding_6_rd_A	27247890	3131	0	0
sealing_sw_binding_7_rd_A	27247890	3140	0	0
sideload_clear_rd_A	27247890	3125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	20833	0	0
T21	12326	0	0	0
T27	29780	451	0	0
T36	9333	0	0	0
T37	13161	0	0	0
T47	0	860	0	0
T48	0	244	0	0
T49	0	79	0	0
T50	0	150	0	0
T51	0	107	0	0
T52	0	622	0	0
T53	0	324	0	0
T54	0	341	0	0
T55	0	485	0	0
T56	11498	0	0	0
T57	35519	0	0	0
T58	1484	0	0	0
T59	10437	0	0	0
T60	4765	0	0	0
T61	6511	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3162	0	0
T49	51256	58	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	25	0	0
T178	0	24	0	0
T179	0	24	0	0
T180	0	78	0	0
T181	0	66	0	0
T182	0	90	0	0
T183	0	60	0	0
T184	0	42	0	0
T185	0	41	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3316	0	0
T49	51256	66	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	21	0	0
T178	0	28	0	0
T179	0	31	0	0
T180	0	65	0	0
T181	0	68	0	0
T182	0	95	0	0
T183	0	62	0	0
T184	0	49	0	0
T185	0	44	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3230	0	0
T49	51256	57	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	16	0	0
T178	0	26	0	0
T179	0	21	0	0
T180	0	65	0	0
T181	0	42	0	0
T182	0	66	0	0
T183	0	94	0	0
T184	0	67	0	0
T185	0	57	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3175	0	0
T49	51256	52	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	14	0	0
T178	0	14	0	0
T179	0	24	0	0
T180	0	42	0	0
T181	0	66	0	0
T182	0	60	0	0
T183	0	43	0	0
T184	0	40	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0
T191	0	3	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3155	0	0
T49	51256	38	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	16	0	0
T178	0	16	0	0
T179	0	22	0	0
T180	0	89	0	0
T181	0	35	0	0
T182	0	54	0	0
T183	0	71	0	0
T184	0	50	0	0
T185	0	63	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3209	0	0
T49	51256	40	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	11	0	0
T178	0	32	0	0
T179	0	32	0	0
T180	0	56	0	0
T181	0	50	0	0
T182	0	80	0	0
T183	0	70	0	0
T184	0	54	0	0
T185	0	58	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3170	0	0
T49	51256	42	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	16	0	0
T178	0	20	0	0
T179	0	19	0	0
T180	0	43	0	0
T181	0	89	0	0
T182	0	64	0	0
T183	0	51	0	0
T184	0	59	0	0
T185	0	51	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3222	0	0
T49	51256	87	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	33	0	0
T180	0	49	0	0
T181	0	55	0	0
T182	0	94	0	0
T183	0	73	0	0
T184	0	31	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0
T192	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	4075	0	0
T21	12326	0	0	0
T37	13161	0	0	0
T49	0	72	0	0
T57	35519	7	0	0
T58	1484	0	0	0
T59	10437	0	0	0
T60	4765	0	0	0
T61	6511	0	0	0
T87	4672	0	0	0
T88	5602	0	0	0
T133	0	39	0	0
T141	0	88	0	0
T155	6493	0	0	0
T177	0	44	0	0
T178	0	61	0	0
T193	0	12	0	0
T194	0	26	0	0
T195	0	12	0	0
T196	0	23	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3133	0	0
T49	51256	50	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	17	0	0
T178	0	26	0	0
T179	0	18	0	0
T180	0	78	0	0
T181	0	56	0	0
T182	0	49	0	0
T183	0	56	0	0
T184	0	87	0	0
T185	0	39	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3130	0	0
T49	51256	37	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	30	0	0
T178	0	22	0	0
T179	0	29	0	0
T180	0	53	0	0
T181	0	45	0	0
T182	0	63	0	0
T183	0	72	0	0
T184	0	45	0	0
T185	0	69	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3109	0	0
T49	51256	58	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	14	0	0
T178	0	41	0	0
T179	0	24	0	0
T180	0	49	0	0
T181	0	67	0	0
T182	0	76	0	0
T183	0	69	0	0
T184	0	36	0	0
T185	0	54	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3136	0	0
T49	51256	59	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	21	0	0
T178	0	31	0	0
T179	0	36	0	0
T180	0	43	0	0
T181	0	71	0	0
T182	0	71	0	0
T183	0	54	0	0
T184	0	34	0	0
T185	0	60	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3333	0	0
T49	51256	44	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	21	0	0
T178	0	28	0	0
T179	0	28	0	0
T180	0	62	0	0
T181	0	70	0	0
T182	0	58	0	0
T183	0	79	0	0
T184	0	58	0	0
T185	0	68	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3272	0	0
T49	51256	67	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	26	0	0
T178	0	25	0	0
T179	0	33	0	0
T180	0	60	0	0
T181	0	72	0	0
T182	0	61	0	0
T183	0	63	0	0
T184	0	48	0	0
T185	0	78	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3053	0	0
T49	51256	32	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	4	0	0
T178	0	32	0	0
T179	0	18	0	0
T180	0	77	0	0
T181	0	58	0	0
T182	0	67	0	0
T183	0	54	0	0
T184	0	43	0	0
T185	0	70	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3141	0	0
T49	51256	49	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	13	0	0
T178	0	25	0	0
T179	0	28	0	0
T180	0	54	0	0
T181	0	44	0	0
T182	0	66	0	0
T183	0	88	0	0
T184	0	41	0	0
T185	0	53	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3228	0	0
T49	51256	27	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	32	0	0
T178	0	31	0	0
T179	0	31	0	0
T180	0	101	0	0
T181	0	28	0	0
T182	0	57	0	0
T183	0	71	0	0
T184	0	64	0	0
T185	0	53	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3117	0	0
T49	51256	55	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	19	0	0
T178	0	14	0	0
T179	0	31	0	0
T180	0	64	0	0
T181	0	68	0	0
T182	0	56	0	0
T183	0	77	0	0
T184	0	59	0	0
T185	0	71	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3277	0	0
T49	51256	57	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	8	0	0
T178	0	25	0	0
T179	0	32	0	0
T180	0	69	0	0
T181	0	50	0	0
T182	0	33	0	0
T183	0	118	0	0
T184	0	65	0	0
T185	0	91	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3222	0	0
T49	51256	44	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	31	0	0
T178	0	32	0	0
T179	0	16	0	0
T180	0	49	0	0
T181	0	61	0	0
T182	0	71	0	0
T183	0	71	0	0
T184	0	62	0	0
T185	0	59	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3192	0	0
T49	51256	38	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	12	0	0
T178	0	29	0	0
T179	0	46	0	0
T180	0	78	0	0
T181	0	46	0	0
T182	0	61	0	0
T183	0	76	0	0
T184	0	51	0	0
T185	0	73	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3128	0	0
T49	51256	57	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	16	0	0
T178	0	35	0	0
T179	0	12	0	0
T180	0	47	0	0
T181	0	86	0	0
T182	0	54	0	0
T183	0	53	0	0
T184	0	59	0	0
T185	0	47	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3324	0	0
T49	51256	61	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	22	0	0
T178	0	23	0	0
T179	0	33	0	0
T180	0	36	0	0
T181	0	43	0	0
T182	0	29	0	0
T183	0	80	0	0
T184	0	68	0	0
T185	0	41	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3147	0	0
T49	51256	54	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	6	0	0
T178	0	29	0	0
T179	0	34	0	0
T180	0	87	0	0
T181	0	43	0	0
T182	0	52	0	0
T183	0	72	0	0
T184	0	46	0	0
T185	0	60	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3090	0	0
T49	51256	45	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	13	0	0
T178	0	30	0	0
T179	0	36	0	0
T180	0	66	0	0
T181	0	59	0	0
T182	0	69	0	0
T183	0	78	0	0
T184	0	63	0	0
T185	0	40	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3137	0	0
T49	51256	60	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	4	0	0
T178	0	12	0	0
T179	0	40	0	0
T180	0	66	0	0
T181	0	54	0	0
T182	0	66	0	0
T183	0	63	0	0
T184	0	50	0	0
T185	0	59	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3201	0	0
T49	51256	61	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	20	0	0
T178	0	26	0	0
T179	0	28	0	0
T180	0	48	0	0
T181	0	50	0	0
T182	0	48	0	0
T183	0	87	0	0
T184	0	57	0	0
T185	0	67	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3131	0	0
T49	51256	48	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	3	0	0
T178	0	42	0	0
T179	0	21	0	0
T180	0	26	0	0
T181	0	49	0	0
T182	0	66	0	0
T183	0	55	0	0
T184	0	63	0	0
T185	0	49	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3140	0	0
T49	51256	30	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	26	0	0
T178	0	36	0	0
T179	0	25	0	0
T180	0	73	0	0
T181	0	77	0	0
T182	0	47	0	0
T183	0	58	0	0
T184	0	61	0	0
T185	0	64	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27247890	3125	0	0
T49	51256	50	0	0
T70	3136	0	0	0
T71	42874	0	0	0
T95	6739	0	0	0
T128	2292	0	0	0
T177	0	28	0	0
T178	0	35	0	0
T179	0	28	0	0
T180	0	42	0	0
T181	0	38	0	0
T182	0	61	0	0
T183	0	74	0	0
T184	0	78	0	0
T186	4509	0	0	0
T187	3663	0	0	0
T188	5979	0	0	0
T189	10518	0	0	0
T190	11364	0	0	0
T197	0	7	0	0