KMAC/MASKED Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.454m	13.400ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	97.182us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	105.811us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.710s	1.043ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.770s	303.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	32.895us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	105.811us	20	20	100.00
		kmac_csr_aliasing	8.770s	303.621us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	34.804us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	45.717us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.879m	572.654ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.663m	39.082ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.654m	970.196ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.919m	390.599ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.022m	171.701ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.279m	51.672ms	50	50	100.00
		kmac_test_vectors_shake_128	1.771h	1.233s	49	50	98.00
		kmac_test_vectors_shake_256	1.475h	2.128s	49	50	98.00
		kmac_test_vectors_kmac	7.890s	2.130ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.720s	1.205ms	50	50	100.00
V2	sideload	kmac_sideload	8.964m	6.100ms	50	50	100.00
V2	app	kmac_app	7.524m	19.335ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.357m	65.249ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.118m	175.131ms	46	50	92.00
V2	error	kmac_error	9.224m	21.981ms	50	50	100.00
V2	key_error	kmac_key_error	9.150s	11.149ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.210s	2.068ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.000s	2.750ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.332m	8.130ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.930s	3.546ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.949m	144.482ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	27.969us	50	50	100.00
V2	alert_test	kmac_alert_test	0.990s	28.483us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.360s	108.864us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.360s	108.864us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	97.182us	5	5	100.00
		kmac_csr_rw	1.260s	105.811us	20	20	100.00
		kmac_csr_aliasing	8.770s	303.621us	5	5	100.00
		kmac_same_csr_outstanding	2.840s	195.400us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	97.182us	5	5	100.00
		kmac_csr_rw	1.260s	105.811us	20	20	100.00
		kmac_csr_aliasing	8.770s	303.621us	5	5	100.00
		kmac_same_csr_outstanding	2.840s	195.400us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.180s	439.579us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.180s	439.579us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.180s	439.579us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.180s	439.579us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.570s	975.903us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.778m	41.617ms	5	5	100.00
		kmac_tl_intg_err	5.350s	1.176ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.350s	1.176ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.930s	3.546ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.454m	13.400ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.964m	6.100ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.180s	439.579us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.778m	41.617ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.778m	41.617ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.778m	41.617ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.454m	13.400ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.930s	3.546ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.778m	41.617ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.692m	5.711ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.454m	13.400ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.027h	120.772ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1268	1290	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	98.40	93.36	99.93	96.36	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:

Test kmac_stress_all_with_rand_reset has 9 failures.

0.kmac_stress_all_with_rand_reset.1680071410
Line 998, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 57367748534 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 57367748534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_stress_all_with_rand_reset.276185846
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  10813538 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @  10813538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 2 failures.

12.kmac_entropy_refresh.3279184318
Line 271, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8959397875 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (197 [0xc5] vs 94 [0x5e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8959397875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_entropy_refresh.697275475
Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8948567483 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 89 [0x59]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8948567483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

33.kmac_app.3958819119
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 1403271327 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (20 [0x14] vs 8 [0x8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1403271327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

36.kmac_stress_all.4044603081
Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log

  UVM_FATAL @ 8560460727 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (26 [0x1a] vs 198 [0xc6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8560460727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:

Test kmac_stress_all_with_rand_reset has 2 failures.

18.kmac_stress_all_with_rand_reset.3527382686
Line 1535, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 213333155122 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 213333155122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.kmac_stress_all_with_rand_reset.4158917412
Line 930, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 46831106750 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 46831106750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

25.kmac_stress_all.1879739042
Line 433, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log

  UVM_FATAL @ 165002162940 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 165002162940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_stress_all.2767607352
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log

  UVM_FATAL @ 74005718079 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 74005718079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_burst_write has 1 failures.

28.kmac_burst_write.3724038428
Line 320, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

35.kmac_entropy_refresh.1698937008
Line 372, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_test_vectors_shake_256 has 1 failures.

33.kmac_test_vectors_shake_256.3593051025
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  39753347 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  39753347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

43.kmac_entropy_refresh.1620090876
Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest/run.log

  UVM_ERROR @ 3976108731 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 3976108731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 34.kmac_test_vectors_shake_128.2039873794
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:2c8d77fa-155e-4bcf-b2af-7e59f1eabae3
```