Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	0.00	0.00	0.00			0.00
u_prim_sec_anchor_buf	0.00	0.00
u_round_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		85	0	0.00
CONT_ASSIGN	134	0	0
ALWAYS	137	3	0	0.00
ALWAYS	143	56	0	0.00
CONT_ASSIGN	309	1	0	0.00
ALWAYS	327	6	0	0.00
CONT_ASSIGN	336	1	0	0.00
ALWAYS	344	7	0	0.00
ALWAYS	366	4	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	403	1	0	0.00
CONT_ASSIGN	404	1	0	0.00
ALWAYS	427	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134		unreachable
137	0	3
143	0	1
145	0	1
146	0	1
147	0	1
149	0	1
150	0	1
152	0	1
154	0	1
155	0	1
157	0	1
159	0	1
161	0	1
163	0	1
165	0	1
167	0	1
168	0	1
169	0	1
174	0	1
176	0	1
177	0	1
179	0	1
180	0	1
182		unreachable
184	0	1
190	0	1
192	0	1
193		unreachable
195		unreachable
196		unreachable
198	0	1
200	0	1
206	0	1
207	0	1
216	0	1
217	0	1
218	0	1
220	0	1
226	0	1
227	0	1
230	0	1
233	0	1
239	0	1
246	0	1
247	0	1
250	0	1
253	0	1
255	0	1
257	0	1
258	0	1
264	0	1
265	0	1
268	0	1
270	0	1
271		unreachable
273		unreachable
274		unreachable
276	0	1
278	0	1
283	0	1
288	0	1
289	0	1
301	0	1
302	0	1
			==> MISSING_ELSE
309	0	1
327	0	1
328	0	1
329	0	1
330	0	1
331	0	1
332	0	1
			==> MISSING_ELSE
336	0	1
344	0	1
345	0	1
346	0	1
347	0	1
351	0	1
352	0	1
355	0	1
			==> MISSING_ELSE
366	0	1
368	0	1
370	0	1
372	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
377	0	1
401	0	1
403	0	1
404	0	1
427	0	1
428	0	1
430	0	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       177
 EXPRESSION (EnMasking && run_i)
             ----1----    --2--

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       216
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       309
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       351
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	0	0.00	(Not included in score)
Transitions	15	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	182	Not Covered
KeccakStError	283	Not Covered
KeccakStIdle	165	Not Covered
KeccakStPhase1	179	Not Covered
KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle3	255	Not Covered
KeccakStTerminalError	302	Not Covered

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	193	Not Covered
KeccakStActive->KeccakStTerminalError	302	Not Covered
KeccakStError->KeccakStTerminalError	302	Not Covered
KeccakStIdle->KeccakStActive	182	Not Covered
KeccakStIdle->KeccakStPhase1	179	Not Covered
KeccakStIdle->KeccakStTerminalError	302	Not Covered
KeccakStPhase1->KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase1->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	255	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle3->KeccakStIdle	271	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	276	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	302	Not Covered

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		31	0	0.00
TERNARY	309	2	0	0.00
IF	137	2	0	0.00
CASE	161	14	0	0.00
IF	301	2	0	0.00
IF	327	4	0	0.00
IF	345	2	0	0.00
IF	368	3	0	0.00
IF	427	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	309	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	161	case (keccak_st)
-2-:	163	if (valid_i)
-3-:	169	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	177	if ((EnMasking && run_i))
-5-:	180	if (((!EnMasking) && run_i))
-6-:	192	if (rnd_eq_end)
-7-:	216	if ((rand_early_i || rand_valid_i))
-8-:	246	if (rand_valid_i)
-9-:	270	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	-	Not Covered
KeccakStIdle	0	1	-	-	-	-	-	-	Not Covered
KeccakStIdle	0	0	1	-	-	-	-	-	Not Covered
KeccakStIdle	0	0	0	1	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	0	-	-	-	-	Not Covered
KeccakStActive	-	-	-	-	1	-	-	-	Unreachable
KeccakStActive	-	-	-	-	0	-	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	1	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	-	Not Covered
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	1	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	0	-	Not Covered
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	301	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	327	if ((!rst_n))
-2-:	329	if (rst_storage)
-3-:	331	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	345	if (xor_message)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	368	if (rst_storage)
-2-:	370	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	427	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered