Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_2share_chi.g_chi_w[0].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[1].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[2].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[3].u_dom	0.00	0.00				0.00
g_2share_chi.g_chi_w[4].u_dom	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		315	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	90	1	0	0.00
CONT_ASSIGN	90	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
CONT_ASSIGN	95	1	0	0.00
ALWAYS	98	3	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
ALWAYS	175	3	0	0.00
ALWAYS	205	13	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	351	1	0	0.00
CONT_ASSIGN	351	1	0	0.00
CONT_ASSIGN	351	1	0	0.00
CONT_ASSIGN	351	1	0	0.00
CONT_ASSIGN	351	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	399	1	0	0.00
CONT_ASSIGN	399	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
ROUTINE	440	0	0
ROUTINE	440	5	0	0.00
ROUTINE	453	0	0
ROUTINE	453	5	0	0.00
ROUTINE	466	4	0	0.00
ROUTINE	486	0	0
ROUTINE	486	10	0	0.00
ROUTINE	555	0	0
ROUTINE	555	4	0	0.00
ROUTINE	624	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	0	2
90	0	2
94	0	1
95	0	1
98	0	1
99	0	1
100	0	1
132	0	2
136	0	2
143	0	1
147	0	1
148	0	1
171	0	1
175	0	1
176	0	1
178	0	1
205	0	1
207	0	1
208	0	1
209	0	1
212	0	1
213	0	1
214	0	1
217	0	1
218	0	1
219	0	1
222	0	1
223	0	1
224	0	1
236	0	1
250	0	5
251	0	5
253	0	5
254	0	5
261	0	5
266	0	5
272	0	5
277	0	5
283	0	5
288	0	5
294	0	5
299	0	5
306	0	5
307	0	5
308	0	5
309	0	5
315	0	5
342	0	5
343	0	5
344	0	5
345	0	5
346	0	5
348	0	5
349	0	5
350	0	5
351	0	5
352	0	5
355	0	5
356	0	5
363	0	25
366	0	25
391	0	2
392	0	2
399	0	2
401	0	48
421	0	1
440	0	1
441	0	1
442	0	1
443	0	1
447	0	1
453	0	1
454	0	1
455	0	1
456	0	1
460	0	1
466	0	1
467	0	1
469	0	1
471	0	1
486	0	1
487	0	1
489	0	1
490	0	1
492	0	1
493	0	1
496	0	1
497	0	1
498	0	1
501	0	1
555	0	1
556	0	1
557	0	1
560	0	1
624	0	1
625	0	1
627	0	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	160	0	0.00
Logical	160	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].a0_l : g_2share_chi.g_chi_w[0].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].a0_l : g_2share_chi.g_chi_w[1].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].a0_l : g_2share_chi.g_chi_w[2].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].a0_l : g_2share_chi.g_chi_w[3].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].a0_l : g_2share_chi.g_chi_w[4].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].a1_l : g_2share_chi.g_chi_w[0].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].a1_l : g_2share_chi.g_chi_w[1].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].a1_l : g_2share_chi.g_chi_w[2].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].a1_l : g_2share_chi.g_chi_w[3].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].a1_l : g_2share_chi.g_chi_w[4].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].b0_l : g_2share_chi.g_chi_w[0].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].b0_l : g_2share_chi.g_chi_w[1].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].b0_l : g_2share_chi.g_chi_w[2].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].b0_l : g_2share_chi.g_chi_w[3].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].b0_l : g_2share_chi.g_chi_w[4].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].b1_l : g_2share_chi.g_chi_w[0].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].b1_l : g_2share_chi.g_chi_w[1].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].b1_l : g_2share_chi.g_chi_w[2].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].b1_l : g_2share_chi.g_chi_w[3].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].b1_l : g_2share_chi.g_chi_w[4].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(0 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(0, 5)])
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(1 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(1, 5)])
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(2 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(2, 5)])
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(3 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(3, 5)])
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(4 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(4, 5)])
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][0][(W - 1):(W / 2)], iota_data[0][0][0][((W / 2) - 1):0]}) : ({iota_data[0][0][0][(W - 1):(W / 2)], state_in[0][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][1][(W - 1):(W / 2)], iota_data[0][0][1][((W / 2) - 1):0]}) : ({iota_data[0][0][1][(W - 1):(W / 2)], state_in[0][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][2][(W - 1):(W / 2)], iota_data[0][0][2][((W / 2) - 1):0]}) : ({iota_data[0][0][2][(W - 1):(W / 2)], state_in[0][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][3][(W - 1):(W / 2)], iota_data[0][0][3][((W / 2) - 1):0]}) : ({iota_data[0][0][3][(W - 1):(W / 2)], state_in[0][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][4][(W - 1):(W / 2)], iota_data[0][0][4][((W / 2) - 1):0]}) : ({iota_data[0][0][4][(W - 1):(W / 2)], state_in[0][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][0][(W - 1):(W / 2)], iota_data[0][1][0][((W / 2) - 1):0]}) : ({iota_data[0][1][0][(W - 1):(W / 2)], state_in[0][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][1][(W - 1):(W / 2)], iota_data[0][1][1][((W / 2) - 1):0]}) : ({iota_data[0][1][1][(W - 1):(W / 2)], state_in[0][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][2][(W - 1):(W / 2)], iota_data[0][1][2][((W / 2) - 1):0]}) : ({iota_data[0][1][2][(W - 1):(W / 2)], state_in[0][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][3][(W - 1):(W / 2)], iota_data[0][1][3][((W / 2) - 1):0]}) : ({iota_data[0][1][3][(W - 1):(W / 2)], state_in[0][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][4][(W - 1):(W / 2)], iota_data[0][1][4][((W / 2) - 1):0]}) : ({iota_data[0][1][4][(W - 1):(W / 2)], state_in[0][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][0][(W - 1):(W / 2)], iota_data[0][2][0][((W / 2) - 1):0]}) : ({iota_data[0][2][0][(W - 1):(W / 2)], state_in[0][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][1][(W - 1):(W / 2)], iota_data[0][2][1][((W / 2) - 1):0]}) : ({iota_data[0][2][1][(W - 1):(W / 2)], state_in[0][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][2][(W - 1):(W / 2)], iota_data[0][2][2][((W / 2) - 1):0]}) : ({iota_data[0][2][2][(W - 1):(W / 2)], state_in[0][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][3][(W - 1):(W / 2)], iota_data[0][2][3][((W / 2) - 1):0]}) : ({iota_data[0][2][3][(W - 1):(W / 2)], state_in[0][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][4][(W - 1):(W / 2)], iota_data[0][2][4][((W / 2) - 1):0]}) : ({iota_data[0][2][4][(W - 1):(W / 2)], state_in[0][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][0][(W - 1):(W / 2)], iota_data[0][3][0][((W / 2) - 1):0]}) : ({iota_data[0][3][0][(W - 1):(W / 2)], state_in[0][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][1][(W - 1):(W / 2)], iota_data[0][3][1][((W / 2) - 1):0]}) : ({iota_data[0][3][1][(W - 1):(W / 2)], state_in[0][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][2][(W - 1):(W / 2)], iota_data[0][3][2][((W / 2) - 1):0]}) : ({iota_data[0][3][2][(W - 1):(W / 2)], state_in[0][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][3][(W - 1):(W / 2)], iota_data[0][3][3][((W / 2) - 1):0]}) : ({iota_data[0][3][3][(W - 1):(W / 2)], state_in[0][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][4][(W - 1):(W / 2)], iota_data[0][3][4][((W / 2) - 1):0]}) : ({iota_data[0][3][4][(W - 1):(W / 2)], state_in[0][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][0][(W - 1):(W / 2)], iota_data[0][4][0][((W / 2) - 1):0]}) : ({iota_data[0][4][0][(W - 1):(W / 2)], state_in[0][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][1][(W - 1):(W / 2)], iota_data[0][4][1][((W / 2) - 1):0]}) : ({iota_data[0][4][1][(W - 1):(W / 2)], state_in[0][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][2][(W - 1):(W / 2)], iota_data[0][4][2][((W / 2) - 1):0]}) : ({iota_data[0][4][2][(W - 1):(W / 2)], state_in[0][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][3][(W - 1):(W / 2)], iota_data[0][4][3][((W / 2) - 1):0]}) : ({iota_data[0][4][3][(W - 1):(W / 2)], state_in[0][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][4][(W - 1):(W / 2)], iota_data[0][4][4][((W / 2) - 1):0]}) : ({iota_data[0][4][4][(W - 1):(W / 2)], state_in[0][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][0][(W - 1):(W / 2)], iota_data[1][0][0][((W / 2) - 1):0]}) : ({iota_data[1][0][0][(W - 1):(W / 2)], state_in[1][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][1][(W - 1):(W / 2)], iota_data[1][0][1][((W / 2) - 1):0]}) : ({iota_data[1][0][1][(W - 1):(W / 2)], state_in[1][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][2][(W - 1):(W / 2)], iota_data[1][0][2][((W / 2) - 1):0]}) : ({iota_data[1][0][2][(W - 1):(W / 2)], state_in[1][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][3][(W - 1):(W / 2)], iota_data[1][0][3][((W / 2) - 1):0]}) : ({iota_data[1][0][3][(W - 1):(W / 2)], state_in[1][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][4][(W - 1):(W / 2)], iota_data[1][0][4][((W / 2) - 1):0]}) : ({iota_data[1][0][4][(W - 1):(W / 2)], state_in[1][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][0][(W - 1):(W / 2)], iota_data[1][1][0][((W / 2) - 1):0]}) : ({iota_data[1][1][0][(W - 1):(W / 2)], state_in[1][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][1][(W - 1):(W / 2)], iota_data[1][1][1][((W / 2) - 1):0]}) : ({iota_data[1][1][1][(W - 1):(W / 2)], state_in[1][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][2][(W - 1):(W / 2)], iota_data[1][1][2][((W / 2) - 1):0]}) : ({iota_data[1][1][2][(W - 1):(W / 2)], state_in[1][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][3][(W - 1):(W / 2)], iota_data[1][1][3][((W / 2) - 1):0]}) : ({iota_data[1][1][3][(W - 1):(W / 2)], state_in[1][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][4][(W - 1):(W / 2)], iota_data[1][1][4][((W / 2) - 1):0]}) : ({iota_data[1][1][4][(W - 1):(W / 2)], state_in[1][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][0][(W - 1):(W / 2)], iota_data[1][2][0][((W / 2) - 1):0]}) : ({iota_data[1][2][0][(W - 1):(W / 2)], state_in[1][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][1][(W - 1):(W / 2)], iota_data[1][2][1][((W / 2) - 1):0]}) : ({iota_data[1][2][1][(W - 1):(W / 2)], state_in[1][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][2][(W - 1):(W / 2)], iota_data[1][2][2][((W / 2) - 1):0]}) : ({iota_data[1][2][2][(W - 1):(W / 2)], state_in[1][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][3][(W - 1):(W / 2)], iota_data[1][2][3][((W / 2) - 1):0]}) : ({iota_data[1][2][3][(W - 1):(W / 2)], state_in[1][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][4][(W - 1):(W / 2)], iota_data[1][2][4][((W / 2) - 1):0]}) : ({iota_data[1][2][4][(W - 1):(W / 2)], state_in[1][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][0][(W - 1):(W / 2)], iota_data[1][3][0][((W / 2) - 1):0]}) : ({iota_data[1][3][0][(W - 1):(W / 2)], state_in[1][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][1][(W - 1):(W / 2)], iota_data[1][3][1][((W / 2) - 1):0]}) : ({iota_data[1][3][1][(W - 1):(W / 2)], state_in[1][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][2][(W - 1):(W / 2)], iota_data[1][3][2][((W / 2) - 1):0]}) : ({iota_data[1][3][2][(W - 1):(W / 2)], state_in[1][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][3][(W - 1):(W / 2)], iota_data[1][3][3][((W / 2) - 1):0]}) : ({iota_data[1][3][3][(W - 1):(W / 2)], state_in[1][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][4][(W - 1):(W / 2)], iota_data[1][3][4][((W / 2) - 1):0]}) : ({iota_data[1][3][4][(W - 1):(W / 2)], state_in[1][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][0][(W - 1):(W / 2)], iota_data[1][4][0][((W / 2) - 1):0]}) : ({iota_data[1][4][0][(W - 1):(W / 2)], state_in[1][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][1][(W - 1):(W / 2)], iota_data[1][4][1][((W / 2) - 1):0]}) : ({iota_data[1][4][1][(W - 1):(W / 2)], state_in[1][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][2][(W - 1):(W / 2)], iota_data[1][4][2][((W / 2) - 1):0]}) : ({iota_data[1][4][2][(W - 1):(W / 2)], state_in[1][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][3][(W - 1):(W / 2)], iota_data[1][4][3][((W / 2) - 1):0]}) : ({iota_data[1][4][3][(W - 1):(W / 2)], state_in[1][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][4][(W - 1):(W / 2)], iota_data[1][4][4][((W / 2) - 1):0]}) : ({iota_data[1][4][4][(W - 1):(W / 2)], state_in[1][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (in == 0)
            ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       492
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       492
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       493
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		164	0	0.00
TERNARY	306	2	0	0.00
TERNARY	307	2	0	0.00
TERNARY	308	2	0	0.00
TERNARY	309	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	306	2	0	0.00
TERNARY	307	2	0	0.00
TERNARY	308	2	0	0.00
TERNARY	309	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	306	2	0	0.00
TERNARY	307	2	0	0.00
TERNARY	308	2	0	0.00
TERNARY	309	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	306	2	0	0.00
TERNARY	307	2	0	0.00
TERNARY	308	2	0	0.00
TERNARY	309	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	306	2	0	0.00
TERNARY	307	2	0	0.00
TERNARY	308	2	0	0.00
TERNARY	309	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
TERNARY	363	2	0	0.00
TERNARY	366	2	0	0.00
CASE	98	3	0	0.00
IF	175	2	0	0.00
CASE	205	5	0	0.00
IF	466	2	0	0.00
TERNARY	492	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	98	case (phase_sel_i)

Branches:

-1-	Status	Tests
MuBi4False	Not Covered
MuBi4True	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	175	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	205	case (cycle_i)

Branches:

-1-	Status	Tests
2'h0	Not Covered
2'h1	Not Covered
2'h2	Not Covered
2'h3	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	466	if ((in == 0))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	492	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered