KMAC/MASKED Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.501m	4.441ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	27.765us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	53.798us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.150s	6.446ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	12.590s	2.496ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.070s	54.612us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	53.798us	20	20	100.00
		kmac_csr_aliasing	12.590s	2.496ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	11.557us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	132.657us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	55.336m	265.668ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.497m	32.000ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.523m	1.698s	49	50	98.00
		kmac_test_vectors_sha3_256	41.719m	1.028s	50	50	100.00
		kmac_test_vectors_sha3_384	32.700m	780.787ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.949m	722.619ms	50	50	100.00
		kmac_test_vectors_shake_128	1.717h	2.133s	49	50	98.00
		kmac_test_vectors_shake_256	1.516h	1.155s	50	50	100.00
		kmac_test_vectors_kmac	7.090s	1.478ms	50	50	100.00
		kmac_test_vectors_kmac_xof	8.370s	762.973us	50	50	100.00
V2	sideload	kmac_sideload	8.292m	98.951ms	50	50	100.00
V2	app	kmac_app	6.624m	12.900ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.085m	74.165ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.852m	53.678ms	49	50	98.00
V2	error	kmac_error	9.062m	83.435ms	50	50	100.00
V2	key_error	kmac_key_error	13.190s	21.510ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.970s	773.336us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.810s	6.718ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.184m	24.690ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.040s	2.815ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.681m	565.479ms	44	50	88.00
V2	intr_test	kmac_intr_test	0.840s	126.732us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	109.326us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.700s	130.824us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.700s	130.824us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	27.765us	5	5	100.00
		kmac_csr_rw	1.220s	53.798us	20	20	100.00
		kmac_csr_aliasing	12.590s	2.496ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	367.843us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	27.765us	5	5	100.00
		kmac_csr_rw	1.220s	53.798us	20	20	100.00
		kmac_csr_aliasing	12.590s	2.496ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	367.843us	20	20	100.00
V2		TOTAL			1033	1050	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	91.974us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	91.974us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	91.974us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	91.974us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.400s	171.226us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.835m	16.596ms	5	5	100.00
		kmac_tl_intg_err	5.780s	5.029ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.780s	5.029ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.040s	2.815ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.501m	4.441ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.292m	98.951ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	91.974us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.835m	16.596ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.835m	16.596ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.835m	16.596ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.501m	4.441ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.040s	2.815ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.835m	16.596ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.397m	10.965ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.501m	4.441ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.037h	368.144ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1256	1290	97.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	17	68.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.03	98.38	93.15	99.93	94.55	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 16 failures:
- Test kmac_stress_all_with_rand_reset has 16 failures.
  - 1.kmac_stress_all_with_rand_reset.73322042371340682516745144414394405276078085552152121634324368364996760491553
    Line 444, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4349970241 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4349970241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.40755156739363341054650420095815101858742953906947578472453525142730861320212
    Line 452, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23041983057 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 23041983057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_app has 3 failures.

2.kmac_app.103605020829118126884157626145894465333088417662460304502124185637579310814536
Line 336, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app/latest/run.log

  UVM_FATAL @ 12803183483 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (163 [0xa3] vs 101 [0x65]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12803183483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_app.567601709372664818190420388228248015265693036238266095829560161880755510506
Line 416, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_app/latest/run.log

  UVM_FATAL @ 19133484618 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (84 [0x54] vs 53 [0x35]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19133484618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app_with_partial_data has 1 failures.

7.kmac_app_with_partial_data.30446225760393086649513010312967973501369342622056154294316304073448810153914
Line 348, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 14249949602 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 216 [0xd8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14249949602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

26.kmac_entropy_refresh.89680134772465869207839479392331743796828687932353138570632709447790233967796
Line 326, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 17376022248 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (48 [0x30] vs 244 [0xf4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17376022248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

38.kmac_stress_all.56734465652252194445264147641808974529889482952725339374661179950038323438328
Line 282, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_FATAL @ 682358906 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (93 [0x5d] vs 219 [0xdb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 682358906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all has 5 failures.
  - 6.kmac_stress_all.82261583532151070533174831633074419506631952314389600949094283606261430836520
    Line 386, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 29713687969 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 29713687969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all.96707417554827353200822565365569533077112577830687606781923188788900245527485
    Line 510, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 55749772812 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 55749772812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 28.kmac_burst_write.29768474505636636402060468447487905094174663456565026416659720308509822810454
    Line 407, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.kmac_burst_write.104416698195436252722951024376707246274129425736608924876135749460127760966835
    Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 40.kmac_test_vectors_shake_128.6279671230852200136018760181943423825014049906302711177985568398709983536070
    Line 1900, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 8.kmac_test_vectors_sha3_384.91214244864079546048963896214103426769843914101176008582323296944467243575857
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  58269213 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  58269213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 37.kmac_smoke.79231915188535529725921205855517958814120076521875146755804909028039403617077
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_smoke/latest/run.log
```
  UVM_ERROR @  55920239 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  55920239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 37.kmac_test_vectors_sha3_224.60536642171887066912659398094225030132159698774480444264820773144783093567354
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  50961297 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  50961297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```