|  |  |  |  |  |  |  |     
    
| gen_alert_tx[0].u_prim_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_alert_tx[1].u_prim_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
gen_entropy.u_entropy  | 
 96.78 | 
100.00 | 
 87.97 | 
100.00 | 
 93.75 | 
 98.98 | 
100.00 | 
    
    
| u_entropy_configured | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_prim_buf.u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_hash_count | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_prim_trivium | 
 95.62 | 
100.00 | 
 88.37 | 
 | 
 | 
 94.12 | 
100.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_entropy.u_prim_sync_reqack_data | 
 95.83 | 
100.00 | 
 83.33 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_prim_sync_reqack | 
 95.83 | 
100.00 | 
 83.33 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| intr_fifo_empty | 
 86.94 | 
 90.00 | 
 77.78 | 
 | 
 | 
 80.00 | 
100.00 | 
    
    
| intr_kmac_done | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| intr_kmac_err | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| kmac_csr_assert | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| sha3pad_assert_cov_if | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| tlul_assert_device | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_app_intf | 
 84.31 | 
 94.07 | 
 88.60 | 
 | 
 46.67 | 
 92.23 | 
100.00 | 
    
    
| u_appid_arb | 
 95.05 | 
 87.50 | 
 92.68 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_prim_buf_state_err_check | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_buf_state_kmac_sel | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_buf_state_output_sel | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_buf_state_output_valid | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_errchk | 
 92.66 | 
 95.18 | 
 94.59 | 
 | 
 80.00 | 
 93.55 | 
100.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
u_kmac_core  | 
 95.80 | 
 98.88 | 
 92.86 | 
100.00 | 
100.00 | 
 91.38 | 
 91.67 | 
    
    
| gen_key_slicer[0].u_key_slicer | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_key_slicer[1].u_key_slicer | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_key_index_count | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_msgfifo | 
 97.43 | 
100.00 | 
 95.83 | 
 94.52 | 
100.00 | 
 94.23 | 
100.00 | 
    
    
| u_msgfifo | 
 98.72 | 
100.00 | 
 93.62 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_packer | 
 96.41 | 
100.00 | 
100.00 | 
 89.74 | 
 | 
 92.31 | 
100.00 | 
    
    
| g_pos_dupcnt.u_pos | 
 89.74 | 
 | 
 | 
 89.74 | 
 | 
 | 
 | 
    
    
| u_prim_lc_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_reg | 
 98.99 | 
 99.25 | 
 96.97 | 
100.00 | 
 | 
 98.72 | 
100.00 | 
    
    
| subtree... | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
    
    
u_sha3  | 
 96.98 | 
 98.85 | 
 95.87 | 
100.00 | 
 90.48 | 
 96.71 | 
100.00 | 
    
    
| u_keccak | 
 94.79 | 
 98.83 | 
 98.84 | 
100.00 | 
 73.33 | 
 97.76 | 
100.00 | 
    
    
| u_keccak_p | 
 99.42 | 
100.00 | 
 98.75 | 
 | 
 | 
 98.93 | 
100.00 | 
    
    
| g_2share_chi.g_chi_w[0].u_dom | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_inner_domain_regs.u_prim_flop_tab01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_flop_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_xor_q01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_xor_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| g_2share_chi.g_chi_w[1].u_dom | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_inner_domain_regs.u_prim_flop_tab01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_flop_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_xor_q01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_xor_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| g_2share_chi.g_chi_w[2].u_dom | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_inner_domain_regs.u_prim_flop_tab01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_flop_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_xor_q01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_xor_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| g_2share_chi.g_chi_w[3].u_dom | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_inner_domain_regs.u_prim_flop_tab01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_flop_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_xor_q01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_xor_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| g_2share_chi.g_chi_w[4].u_dom | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_inner_domain_regs.u_prim_flop_tab01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_flop_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_xor_q01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_xor_t01 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_sec_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_round_count | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
u_pad  | 
 97.27 | 
 99.45 | 
 88.37 | 
100.00 | 
100.00 | 
 95.79 | 
100.00 | 
    
    
| u_prefix_slicer | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_sentmsg_count | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sha3_done_sender | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_prim_buf.u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_staterd | 
 89.90 | 
 89.96 | 
 81.09 | 
 | 
 | 
 88.54 | 
100.00 | 
    
    
| gen_slicer[0].u_state_slice | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_slicer[1].u_state_slice | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_tlul_adapter | 
 89.67 | 
 89.39 | 
 81.51 | 
 | 
 | 
 87.78 | 
100.00 | 
    
    
| u_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_reqfifo | 
 88.33 | 
 95.00 | 
 75.00 | 
 | 
 | 
 83.33 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 81.58 | 
 92.00 | 
 80.00 | 
 | 
 | 
 72.73 | 
 | 
    
    
| u_rsp_gen | 
 91.67 | 
 83.33 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rspfifo | 
 89.32 | 
 95.00 | 
 77.27 | 
 | 
 | 
 85.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 81.58 | 
 92.00 | 
 80.00 | 
 | 
 | 
 72.73 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_sramreqfifo | 
 87.64 | 
 95.00 | 
 72.22 | 
 | 
 | 
 83.33 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 81.58 | 
 92.00 | 
 80.00 | 
 | 
 | 
 72.73 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_adapter_msgfifo | 
 80.11 | 
 87.12 | 
 74.69 | 
 | 
 | 
 77.38 | 
 81.25 | 
    
    
| u_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_reqfifo | 
 88.33 | 
 95.00 | 
 75.00 | 
 | 
 | 
 83.33 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 81.58 | 
 92.00 | 
 80.00 | 
 | 
 | 
 72.73 | 
 | 
    
    
| u_rsp_gen | 
 91.67 | 
 83.33 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rspfifo | 
 69.33 | 
 91.43 | 
 57.14 | 
 | 
 | 
 68.75 | 
 60.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 71.04 | 
 90.91 | 
 66.67 | 
 | 
 | 
 55.56 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_sramreqfifo | 
 65.86 | 
 86.11 | 
 54.84 | 
 | 
 | 
 62.50 | 
 60.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 71.04 | 
 90.91 | 
 66.67 | 
 | 
 | 
 55.56 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 |