Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1341224751	33292	0	0
entropy_period_rd_A	1341224751	2214	0	0
intr_enable_rd_A	1341224751	2960	0	0
prefix_0_rd_A	1341224751	2111	0	0
prefix_10_rd_A	1341224751	2065	0	0
prefix_1_rd_A	1341224751	2228	0	0
prefix_2_rd_A	1341224751	2240	0	0
prefix_3_rd_A	1341224751	2073	0	0
prefix_4_rd_A	1341224751	2142	0	0
prefix_5_rd_A	1341224751	2096	0	0
prefix_6_rd_A	1341224751	2076	0	0
prefix_7_rd_A	1341224751	2193	0	0
prefix_8_rd_A	1341224751	2249	0	0
prefix_9_rd_A	1341224751	2112	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	33292	0	0
T22	565189	30173	0	0
T94	0	3	0	0
T95	0	81	0	0
T113	0	86	0	0
T115	0	172	0	0
T116	0	1	0	0
T118	0	4	0	0
T123	0	55	0	0
T128	0	7	0	0
T129	0	140	0	0
T132	109654	0	0	0
T133	3806	0	0	0
T134	193576	0	0	0
T135	881704	0	0	0
T136	114538	0	0	0
T137	165459	0	0	0
T138	724485	0	0	0
T139	12373	0	0	0
T140	345411	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2214	0	0
T78	6051	27	0	0
T84	1742	1	0	0
T85	4440	15	0	0
T88	12163	36	0	0
T118	22450	74	0	0
T130	4453	2	0	0
T152	2711	8	0	0
T153	1950	9	0	0
T154	3404	3	0	0
T155	4866	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2960	0	0
T78	6051	56	0	0
T84	1742	1	0	0
T85	4440	26	0	0
T88	12163	97	0	0
T118	22450	153	0	0
T130	4453	18	0	0
T152	2711	11	0	0
T153	1950	18	0	0
T156	1363	5	0	0
T157	1257	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2111	0	0
T78	6051	23	0	0
T84	1742	9	0	0
T85	4440	26	0	0
T88	12163	50	0	0
T118	22450	81	0	0
T125	14531	2	0	0
T130	4453	5	0	0
T152	2711	11	0	0
T153	1950	4	0	0
T154	3404	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2065	0	0
T78	6051	19	0	0
T84	1742	5	0	0
T85	4440	12	0	0
T88	12163	57	0	0
T118	22450	70	0	0
T130	4453	4	0	0
T152	2711	7	0	0
T153	1950	7	0	0
T154	3404	11	0	0
T155	4866	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2228	0	0
T78	6051	14	0	0
T85	4440	13	0	0
T88	12163	41	0	0
T118	22450	82	0	0
T130	4453	2	0	0
T152	2711	2	0	0
T153	1950	5	0	0
T154	3404	16	0	0
T155	4866	10	0	0
T158	7770	12	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2240	0	0
T78	6051	41	0	0
T84	1742	2	0	0
T85	4440	22	0	0
T88	12163	61	0	0
T118	22450	70	0	0
T130	4453	14	0	0
T152	2711	8	0	0
T153	1950	1	0	0
T154	3404	8	0	0
T155	4866	12	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2073	0	0
T78	6051	23	0	0
T84	1742	6	0	0
T85	4440	12	0	0
T88	12163	35	0	0
T118	22450	77	0	0
T130	4453	10	0	0
T152	2711	6	0	0
T153	1950	1	0	0
T154	3404	6	0	0
T155	4866	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2142	0	0
T78	6051	22	0	0
T84	1742	2	0	0
T85	4440	18	0	0
T88	12163	51	0	0
T118	22450	112	0	0
T130	4453	5	0	0
T152	2711	15	0	0
T153	1950	2	0	0
T154	3404	8	0	0
T155	4866	12	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2096	0	0
T78	6051	31	0	0
T84	1742	6	0	0
T85	4440	11	0	0
T88	12163	46	0	0
T118	22450	81	0	0
T130	4453	1	0	0
T152	2711	13	0	0
T154	3404	6	0	0
T155	4866	15	0	0
T158	7770	18	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2076	0	0
T78	6051	22	0	0
T84	1742	7	0	0
T85	4440	25	0	0
T88	12163	46	0	0
T118	22450	87	0	0
T130	4453	13	0	0
T152	2711	13	0	0
T153	1950	4	0	0
T154	3404	12	0	0
T155	4866	11	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2193	0	0
T78	6051	29	0	0
T84	1742	5	0	0
T85	4440	15	0	0
T88	12163	59	0	0
T118	22450	77	0	0
T125	14531	5	0	0
T130	4453	16	0	0
T152	2711	17	0	0
T153	1950	2	0	0
T154	3404	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2249	0	0
T78	6051	21	0	0
T84	1742	7	0	0
T85	4440	28	0	0
T88	12163	46	0	0
T118	22450	83	0	0
T125	14531	6	0	0
T130	4453	4	0	0
T152	2711	6	0	0
T153	1950	3	0	0
T154	3404	12	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1341224751	2112	0	0
T78	6051	12	0	0
T84	1742	1	0	0
T85	4440	17	0	0
T88	12163	47	0	0
T118	22450	77	0	0
T125	14531	9	0	0
T130	4453	18	0	0
T152	2711	10	0	0
T153	1950	6	0	0
T154	3404	11	0	0